^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2019 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Wendell Lin <wendell.lin@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <dt-bindings/clock/mt6779-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) static const struct mtk_gate_regs img_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) .set_ofs = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) .clr_ofs = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) .sta_ofs = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define GATE_IMG(_id, _name, _parent, _shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) &mtk_clk_gate_ops_setclr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static const struct mtk_gate img_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) GATE_IMG(CLK_IMG_LARB5, "imgsys_larb5", "img_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) GATE_IMG(CLK_IMG_LARB6, "imgsys_larb6", "img_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) GATE_IMG(CLK_IMG_DIP, "imgsys_dip", "img_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) GATE_IMG(CLK_IMG_MFB, "imgsys_mfb", "img_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) GATE_IMG(CLK_IMG_WPE_A, "imgsys_wpe_a", "img_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static const struct of_device_id of_match_clk_mt6779_img[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) { .compatible = "mediatek,mt6779-imgsys", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int clk_mt6779_img_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static struct platform_driver clk_mt6779_img_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .probe = clk_mt6779_img_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .name = "clk-mt6779-img",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .of_match_table = of_match_clk_mt6779_img,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) builtin_platform_driver(clk_mt6779_img_drv);