Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2019 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Author: Wendell Lin <wendell.lin@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <dt-bindings/clock/mt6779-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) static const struct mtk_gate_regs cam_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	.set_ofs = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	.clr_ofs = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	.sta_ofs = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define GATE_CAM(_id, _name, _parent, _shift)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		&mtk_clk_gate_ops_setclr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static const struct mtk_gate cam_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	GATE_CAM(CLK_CAM_LARB10, "camsys_larb10", "cam_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	GATE_CAM(CLK_CAM_DFP_VAD, "camsys_dfp_vad", "cam_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	GATE_CAM(CLK_CAM_LARB11, "camsys_larb11", "cam_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	GATE_CAM(CLK_CAM_LARB9, "camsys_larb9", "cam_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	GATE_CAM(CLK_CAM_CAM, "camsys_cam", "cam_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	GATE_CAM(CLK_CAM_CAMTG, "camsys_camtg", "cam_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	GATE_CAM(CLK_CAM_SENINF, "camsys_seninf", "cam_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	GATE_CAM(CLK_CAM_CAMSV0, "camsys_camsv0", "cam_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	GATE_CAM(CLK_CAM_CAMSV1, "camsys_camsv1", "cam_sel", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	GATE_CAM(CLK_CAM_CAMSV2, "camsys_camsv2", "cam_sel", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	GATE_CAM(CLK_CAM_CAMSV3, "camsys_camsv3", "cam_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	GATE_CAM(CLK_CAM_CCU, "camsys_ccu", "cam_sel", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	GATE_CAM(CLK_CAM_FAKE_ENG, "camsys_fake_eng", "cam_sel", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static const struct of_device_id of_match_clk_mt6779_cam[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	{ .compatible = "mediatek,mt6779-camsys", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static int clk_mt6779_cam_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	clk_data = mtk_alloc_clk_data(CLK_CAM_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	mtk_clk_register_gates(node, cam_clks, ARRAY_SIZE(cam_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 			       clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static struct platform_driver clk_mt6779_cam_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	.probe = clk_mt6779_cam_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		.name = "clk-mt6779-cam",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		.of_match_table = of_match_clk_mt6779_cam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) builtin_platform_driver(clk_mt6779_cam_drv);