^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2019 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Wendell Lin <wendell.lin@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <dt-bindings/clock/mt6779-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static const struct mtk_gate_regs audio0_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) .set_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) .clr_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .sta_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static const struct mtk_gate_regs audio1_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .set_ofs = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .clr_ofs = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .sta_ofs = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GATE_AUDIO0(_id, _name, _parent, _shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) &mtk_clk_gate_ops_no_setclr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define GATE_AUDIO1(_id, _name, _parent, _shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) &mtk_clk_gate_ops_no_setclr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static const struct mtk_gate audio_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* AUDIO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) GATE_AUDIO0(CLK_AUD_AFE, "aud_afe", "audio_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) GATE_AUDIO0(CLK_AUD_22M, "aud_22m", "aud_eng1_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) GATE_AUDIO0(CLK_AUD_24M, "aud_24m", "aud_eng2_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) GATE_AUDIO0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) "aud_eng2_sel", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) GATE_AUDIO0(CLK_AUD_APLL_TUNER, "aud_apll_tuner",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "aud_eng1_sel", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) GATE_AUDIO0(CLK_AUD_TDM, "aud_tdm", "aud_eng1_sel", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) GATE_AUDIO0(CLK_AUD_ADC, "aud_adc", "audio_sel", 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) GATE_AUDIO0(CLK_AUD_DAC, "aud_dac", "audio_sel", 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) GATE_AUDIO0(CLK_AUD_DAC_PREDIS, "aud_dac_predis",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) "audio_sel", 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) GATE_AUDIO0(CLK_AUD_TML, "aud_tml", "audio_sel", 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) GATE_AUDIO0(CLK_AUD_NLE, "aud_nle", "audio_sel", 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* AUDIO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) GATE_AUDIO1(CLK_AUD_I2S1_BCLK_SW, "aud_i2s1_bclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) "audio_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) GATE_AUDIO1(CLK_AUD_I2S2_BCLK_SW, "aud_i2s2_bclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) "audio_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) GATE_AUDIO1(CLK_AUD_I2S3_BCLK_SW, "aud_i2s3_bclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) "audio_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) GATE_AUDIO1(CLK_AUD_I2S4_BCLK_SW, "aud_i2s4_bclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) "audio_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) GATE_AUDIO1(CLK_AUD_I2S5_BCLK_SW, "aud_i2s5_bclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) "audio_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) GATE_AUDIO1(CLK_AUD_CONN_I2S_ASRC, "aud_conn_i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "audio_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) GATE_AUDIO1(CLK_AUD_GENERAL1_ASRC, "aud_general1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) "audio_sel", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) GATE_AUDIO1(CLK_AUD_GENERAL2_ASRC, "aud_general2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) "audio_sel", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) GATE_AUDIO1(CLK_AUD_DAC_HIRES, "aud_dac_hires",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) "audio_h_sel", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) GATE_AUDIO1(CLK_AUD_ADC_HIRES, "aud_adc_hires",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) "audio_h_sel", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) GATE_AUDIO1(CLK_AUD_ADC_HIRES_TML, "aud_adc_hires_tml",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "audio_h_sel", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) GATE_AUDIO1(CLK_AUD_PDN_ADDA6_ADC, "aud_pdn_adda6_adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) "audio_sel", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) GATE_AUDIO1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "audio_h_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) GATE_AUDIO1(CLK_AUD_3RD_DAC, "aud_3rd_dac", "audio_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) GATE_AUDIO1(CLK_AUD_3RD_DAC_PREDIS, "aud_3rd_dac_predis",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "audio_sel", 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) GATE_AUDIO1(CLK_AUD_3RD_DAC_TML, "aud_3rd_dac_tml",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) "audio_sel", 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) GATE_AUDIO1(CLK_AUD_3RD_DAC_HIRES, "aud_3rd_dac_hires",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "audio_h_sel", 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static const struct of_device_id of_match_clk_mt6779_aud[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { .compatible = "mediatek,mt6779-audio", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int clk_mt6779_aud_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static struct platform_driver clk_mt6779_aud_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .probe = clk_mt6779_aud_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .name = "clk-mt6779-aud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .of_match_table = of_match_clk_mt6779_aud,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) builtin_platform_driver(clk_mt6779_aud_drv);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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