^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Owen Chen <owen.chen@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "clk-mux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <dt-bindings/clock/mt6765-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*fmeter div select 4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define _DIV4_ 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static DEFINE_SPINLOCK(mt6765_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Total 12 subsys */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static void __iomem *cksys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static void __iomem *apmixed_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* CKSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLK_SCP_CFG_0 (cksys_base + 0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLK_SCP_CFG_1 (cksys_base + 0x204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* CG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AP_PLL_CON3 (apmixed_base + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PLLON_CON0 (apmixed_base + 0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PLLON_CON1 (apmixed_base + 0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* clk cfg update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLK_CFG_0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLK_CFG_0_SET 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLK_CFG_0_CLR 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLK_CFG_1 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLK_CFG_1_SET 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLK_CFG_1_CLR 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLK_CFG_2 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CLK_CFG_2_SET 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLK_CFG_2_CLR 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLK_CFG_3 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLK_CFG_3_SET 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLK_CFG_3_CLR 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLK_CFG_4 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CLK_CFG_4_SET 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLK_CFG_4_CLR 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CLK_CFG_5 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CLK_CFG_5_SET 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CLK_CFG_5_CLR 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CLK_CFG_6 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CLK_CFG_6_SET 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CLK_CFG_6_CLR 0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CLK_CFG_7 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CLK_CFG_7_SET 0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CLK_CFG_7_CLR 0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CLK_CFG_8 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CLK_CFG_8_SET 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CLK_CFG_8_CLR 0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CLK_CFG_9 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CLK_CFG_9_SET 0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CLK_CFG_9_CLR 0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CLK_CFG_10 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CLK_CFG_10_SET 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CLK_CFG_10_CLR 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CLK_CFG_UPDATE 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static const struct mtk_fixed_clk fixed_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) FIXED_CLK(CLK_TOP_F_FRTC, "f_frtc_ck", "clk32k", 32768),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) FIXED_CLK(CLK_TOP_CLK26M, "clk_26m_ck", "clk26m", 26000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 466000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const struct mtk_fixed_factor top_divs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) FACTOR(CLK_TOP_USB20_192M, "usb20_192m_ck", "univpll", 2, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) FACTOR(CLK_TOP_USB20_192M_D4, "usb20_192m_d4", "usb20_192m_ck", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) FACTOR(CLK_TOP_USB20_192M_D8, "usb20_192m_d8", "usb20_192m_ck", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) FACTOR(CLK_TOP_USB20_192M_D16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "usb20_192m_d16", "usb20_192m_ck", 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) FACTOR(CLK_TOP_USB20_192M_D32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "usb20_192m_d32", "usb20_192m_ck", 1, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll_d3", 1, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) FACTOR(CLK_TOP_MPLL, "mpll_ck", "mpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) FACTOR(CLK_TOP_DA_MPLL_104M_DIV, "mpll_104m_div", "mpll_ck", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) FACTOR(CLK_TOP_DA_MPLL_52M_DIV, "mpll_52m_div", "mpll_ck", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", "mfgpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) FACTOR(CLK_TOP_ULPOSC1, "ulposc1_ck", "ulposc1", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) FACTOR(CLK_TOP_ULPOSC1_D2, "ulposc1_d2", "ulposc1_ck", 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) FACTOR(CLK_TOP_ULPOSC1_D4, "ulposc1_d4", "ulposc1_ck", 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) FACTOR(CLK_TOP_ULPOSC1_D8, "ulposc1_d8", "ulposc1_ck", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) FACTOR(CLK_TOP_ULPOSC1_D16, "ulposc1_d16", "ulposc1_ck", 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) FACTOR(CLK_TOP_ULPOSC1_D32, "ulposc1_d32", "ulposc1_ck", 1, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) FACTOR(CLK_TOP_F_F26M, "f_f26m_ck", "clk_26m_ck", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) FACTOR(CLK_TOP_AXI, "axi_ck", "axi_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) FACTOR(CLK_TOP_MM, "mm_ck", "mm_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) FACTOR(CLK_TOP_SCP, "scp_ck", "scp_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) FACTOR(CLK_TOP_MFG, "mfg_ck", "mfg_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) FACTOR(CLK_TOP_F_FUART, "f_fuart_ck", "uart_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) FACTOR(CLK_TOP_SPI, "spi_ck", "spi_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) FACTOR(CLK_TOP_MSDC50_0, "msdc50_0_ck", "msdc50_0_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) FACTOR(CLK_TOP_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) FACTOR(CLK_TOP_AUDIO, "audio_ck", "audio_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) FACTOR(CLK_TOP_AUD_1, "aud_1_ck", "aud_1_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) FACTOR(CLK_TOP_AUD_ENGEN1, "aud_engen1_ck", "aud_engen1_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) FACTOR(CLK_TOP_F_FDISP_PWM, "f_fdisp_pwm_ck", "disp_pwm_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) FACTOR(CLK_TOP_SSPM, "sspm_ck", "sspm_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) FACTOR(CLK_TOP_DXCC, "dxcc_ck", "dxcc_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) FACTOR(CLK_TOP_I2C, "i2c_ck", "i2c_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) FACTOR(CLK_TOP_F_FPWM, "f_fpwm_ck", "pwm_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) FACTOR(CLK_TOP_F_FSENINF, "f_fseninf_ck", "seninf_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) FACTOR(CLK_TOP_AES_FDE, "aes_fde_ck", "aes_fde_sel", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) FACTOR(CLK_TOP_F_BIST2FPC, "f_bist2fpc_ck", "univpll2_d2", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) FACTOR(CLK_TOP_ARMPLL_DIVIDER_PLL0, "arm_div_pll0", "syspll_d2", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) FACTOR(CLK_TOP_ARMPLL_DIVIDER_PLL1, "arm_div_pll1", "syspll_ck", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) FACTOR(CLK_TOP_ARMPLL_DIVIDER_PLL2, "arm_div_pll2", "univpll_d2", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) FACTOR(CLK_TOP_DA_USB20_48M_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "usb20_48m_div", "usb20_192m_d4", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) FACTOR(CLK_TOP_DA_UNIV_48M_DIV, "univ_48m_div", "usb20_192m_d4", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const char * const axi_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) "syspll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "syspll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) "syspll3_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const char * const mem_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) "dmpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "apll1_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const char * const mm_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) "mmpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) "syspll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) "syspll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "mmpll_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const char * const scp_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) "syspll4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) "syspll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) "univpll_d3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static const char * const mfg_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "mfgpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) "syspll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) "univpll_d3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const char * const atb_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "syspll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "syspll1_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const char * const camtg_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "usb20_192m_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "univpll2_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) "usb20_192m_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "univpll2_d32",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) "usb20_192m_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) "usb20_192m_d32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const char * const uart_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) "univpll2_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const char * const spi_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) "syspll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) "syspll4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "syspll2_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const char * const msdc5hclk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) "univpll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) "syspll2_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const char * const msdc50_0_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) "msdcpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) "syspll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) "syspll4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) "univpll1_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static const char * const msdc30_1_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) "msdcpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) "syspll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) "syspll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) "univpll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) "usb20_192m_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) "syspll2_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static const char * const audio_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) "syspll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) "syspll4_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) "syspll1_d16"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const char * const aud_intbus_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "syspll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) "syspll4_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static const char * const aud_1_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) "apll1_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static const char * const aud_engen1_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) "apll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) "apll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) "apll1_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static const char * const disp_pwm_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) "ulposc1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) "ulposc1_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static const char * const sspm_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) "syspll_d3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const char * const dxcc_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) "syspll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) "syspll1_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const char * const usb_top_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "univpll3_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static const char * const spm_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) "syspll1_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static const char * const i2c_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) "univpll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) "univpll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) "syspll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) "syspll2_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static const char * const pwm_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) "univpll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) "syspll1_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static const char * const seninf_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) "univpll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) "univpll2_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const char * const aes_fde_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) "msdcpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) "syspll1_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const char * const ulposc_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) "ulposc1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) "ulposc1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) "ulposc1_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) "ulposc1_d32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const char * const camtm_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) "univpll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) "univpll2_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define INVALID_UPDATE_REG 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define INVALID_UPDATE_SHIFT -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define INVALID_MUX_GATE -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static const struct mtk_mux top_muxes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* CLK_CFG_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 0, 2, 7, CLK_CFG_UPDATE, 0, CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 8, 2, 15, CLK_CFG_UPDATE, 1, CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, CLK_CFG_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 3, 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) CLK_CFG_UPDATE, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, CLK_CFG_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) CLK_CFG_0_SET, CLK_CFG_0_CLR, 24, 3, 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) CLK_CFG_UPDATE, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* CLK_CFG_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, CLK_CFG_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) CLK_CFG_1_SET, CLK_CFG_1_CLR, 0, 2, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) CLK_CFG_UPDATE, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, CLK_CFG_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) CLK_CFG_1_SET, CLK_CFG_1_CLR, 8, 2, 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) CLK_CFG_UPDATE, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) camtg_parents, CLK_CFG_1, CLK_CFG_1_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) CLK_CFG_1_CLR, 16, 3, 23, CLK_CFG_UPDATE, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1_SEL, "camtg1_sel", camtg_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 24, 3, 31, CLK_CFG_UPDATE, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* CLK_CFG_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, "camtg2_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) camtg_parents, CLK_CFG_2, CLK_CFG_2_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) CLK_CFG_2_CLR, 0, 3, 7, CLK_CFG_UPDATE, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3_SEL, "camtg3_sel", camtg_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 8, 3, 15, CLK_CFG_UPDATE, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR, 16, 1, 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) CLK_CFG_UPDATE, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, CLK_CFG_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) CLK_CFG_2_SET, CLK_CFG_2_CLR, 24, 2, 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) CLK_CFG_UPDATE, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* CLK_CFG_3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc5hclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) msdc5hclk_parents, CLK_CFG_3, CLK_CFG_3_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) CLK_CFG_3_CLR, 0, 2, 7, CLK_CFG_UPDATE, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) msdc50_0_parents, CLK_CFG_3, CLK_CFG_3_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) CLK_CFG_3_CLR, 8, 3, 15, CLK_CFG_UPDATE, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) msdc30_1_parents, CLK_CFG_3, CLK_CFG_3_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) CLK_CFG_3_CLR, 16, 3, 23, CLK_CFG_UPDATE, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 24, 2, 31, CLK_CFG_UPDATE, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* CLK_CFG_4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) aud_intbus_parents, CLK_CFG_4, CLK_CFG_4_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) CLK_CFG_4_CLR, 0, 2, 7, CLK_CFG_UPDATE, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 8, 1, 15, CLK_CFG_UPDATE, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) aud_engen1_parents, CLK_CFG_4, CLK_CFG_4_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) CLK_CFG_4_CLR, 16, 2, 23, CLK_CFG_UPDATE, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) disp_pwm_parents, CLK_CFG_4, CLK_CFG_4_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) CLK_CFG_4_CLR, 24, 2, 31, CLK_CFG_UPDATE, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* CLK_CFG_5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPM_SEL, "sspm_sel", sspm_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 0, 2, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) CLK_CFG_UPDATE, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel", dxcc_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 8, 2, 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) CLK_CFG_UPDATE, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_SEL, "usb_top_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) usb_top_parents, CLK_CFG_5, CLK_CFG_5_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) CLK_CFG_5_CLR, 16, 1, 23, CLK_CFG_UPDATE, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MUX_GATE_CLR_SET_UPD(CLK_TOP_SPM_SEL, "spm_sel", spm_parents, CLK_CFG_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) CLK_CFG_5_SET, CLK_CFG_5_CLR, 24, 1, 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) CLK_CFG_UPDATE, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* CLK_CFG_6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, CLK_CFG_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) CLK_CFG_6_SET, CLK_CFG_6_CLR, 0, 3, 7, CLK_CFG_UPDATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, CLK_CFG_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) CLK_CFG_6_SET, CLK_CFG_6_CLR, 8, 2, 15, CLK_CFG_UPDATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel", seninf_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, 16, 2, 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) CLK_CFG_UPDATE, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_FDE_SEL, "aes_fde_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) aes_fde_parents, CLK_CFG_6, CLK_CFG_6_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) CLK_CFG_6_CLR, 24, 3, 31, CLK_CFG_UPDATE, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* CLK_CFG_7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_PWRAP_ULPOSC_SEL, "ulposc_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ulposc_parents, CLK_CFG_7, CLK_CFG_7_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) CLK_CFG_7_CLR, 0, 3, 7, CLK_CFG_UPDATE, 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel", camtm_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, 8, 2, 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) CLK_CFG_UPDATE, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static const struct mtk_gate_regs top0_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .set_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .clr_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .sta_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static const struct mtk_gate_regs top1_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .set_ofs = 0x104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .clr_ofs = 0x104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .sta_ofs = 0x104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static const struct mtk_gate_regs top2_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .set_ofs = 0x320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .clr_ofs = 0x320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .sta_ofs = 0x320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define GATE_TOP0(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .regs = &top0_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .ops = &mtk_clk_gate_ops_no_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define GATE_TOP1(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .regs = &top1_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .ops = &mtk_clk_gate_ops_no_setclr_inv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define GATE_TOP2(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .regs = &top2_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .ops = &mtk_clk_gate_ops_no_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static const struct mtk_gate top_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* TOP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) GATE_TOP0(CLK_TOP_MD_32K, "md_32k", "f_frtc_ck", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) GATE_TOP0(CLK_TOP_MD_26M, "md_26m", "f_f26m_ck", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) GATE_TOP0(CLK_TOP_MD2_32K, "md2_32k", "f_frtc_ck", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) GATE_TOP0(CLK_TOP_MD2_26M, "md2_26m", "f_f26m_ck", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* TOP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) GATE_TOP1(CLK_TOP_ARMPLL_DIVIDER_PLL0_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) "arm_div_pll0_en", "arm_div_pll0", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) GATE_TOP1(CLK_TOP_ARMPLL_DIVIDER_PLL1_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) "arm_div_pll1_en", "arm_div_pll1", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) GATE_TOP1(CLK_TOP_ARMPLL_DIVIDER_PLL2_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) "arm_div_pll2_en", "arm_div_pll2", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) GATE_TOP1(CLK_TOP_FMEM_OCC_DRC_EN, "drc_en", "univpll2_d2", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) GATE_TOP1(CLK_TOP_USB20_48M_EN, "usb20_48m_en", "usb20_48m_div", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, "univpll_48m_en", "univ_48m_div", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) GATE_TOP1(CLK_TOP_F_UFS_MP_SAP_CFG_EN, "ufs_sap", "f_f26m_ck", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) GATE_TOP1(CLK_TOP_F_BIST2FPC_EN, "bist2fpc", "f_bist2fpc_ck", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* TOP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) GATE_TOP2(CLK_TOP_APLL12_DIV0, "apll12_div0", "aud_1_ck", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) GATE_TOP2(CLK_TOP_APLL12_DIV1, "apll12_div1", "aud_1_ck", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) GATE_TOP2(CLK_TOP_APLL12_DIV2, "apll12_div2", "aud_1_ck", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) GATE_TOP2(CLK_TOP_APLL12_DIV3, "apll12_div3", "aud_1_ck", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static const struct mtk_gate_regs ifr2_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .set_ofs = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .clr_ofs = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .sta_ofs = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static const struct mtk_gate_regs ifr3_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .set_ofs = 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .clr_ofs = 0x8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .sta_ofs = 0x94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static const struct mtk_gate_regs ifr4_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .set_ofs = 0xa4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .clr_ofs = 0xa8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .sta_ofs = 0xac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static const struct mtk_gate_regs ifr5_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .set_ofs = 0xc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .clr_ofs = 0xc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .sta_ofs = 0xc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define GATE_IFR2(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .regs = &ifr2_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define GATE_IFR3(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .regs = &ifr3_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define GATE_IFR4(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .regs = &ifr4_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define GATE_IFR5(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .regs = &ifr5_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static const struct mtk_gate ifr_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* INFRA_TOPAXI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* INFRA PERI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* INFRA mode 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) GATE_IFR2(CLK_IFR_ICUSB, "ifr_icusb", "axi_ck", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) GATE_IFR2(CLK_IFR_GCE, "ifr_gce", "axi_ck", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) GATE_IFR2(CLK_IFR_THERM, "ifr_therm", "axi_ck", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) GATE_IFR2(CLK_IFR_I2C_AP, "ifr_i2c_ap", "i2c_ck", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) GATE_IFR2(CLK_IFR_I2C_CCU, "ifr_i2c_ccu", "i2c_ck", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) GATE_IFR2(CLK_IFR_I2C_SSPM, "ifr_i2c_sspm", "i2c_ck", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) GATE_IFR2(CLK_IFR_I2C_RSV, "ifr_i2c_rsv", "i2c_ck", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) GATE_IFR2(CLK_IFR_PWM_HCLK, "ifr_pwm_hclk", "axi_ck", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) GATE_IFR2(CLK_IFR_PWM1, "ifr_pwm1", "f_fpwm_ck", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) GATE_IFR2(CLK_IFR_PWM2, "ifr_pwm2", "f_fpwm_ck", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) GATE_IFR2(CLK_IFR_PWM3, "ifr_pwm3", "f_fpwm_ck", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) GATE_IFR2(CLK_IFR_PWM4, "ifr_pwm4", "f_fpwm_ck", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) GATE_IFR2(CLK_IFR_PWM5, "ifr_pwm5", "f_fpwm_ck", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) GATE_IFR2(CLK_IFR_PWM, "ifr_pwm", "f_fpwm_ck", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) GATE_IFR2(CLK_IFR_UART0, "ifr_uart0", "f_fuart_ck", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) GATE_IFR2(CLK_IFR_UART1, "ifr_uart1", "f_fuart_ck", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) GATE_IFR2(CLK_IFR_GCE_26M, "ifr_gce_26m", "f_f26m_ck", 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) GATE_IFR2(CLK_IFR_CQ_DMA_FPC, "ifr_dma", "axi_ck", 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) GATE_IFR2(CLK_IFR_BTIF, "ifr_btif", "axi_ck", 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* INFRA mode 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) GATE_IFR3(CLK_IFR_SPI0, "ifr_spi0", "spi_ck", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) GATE_IFR3(CLK_IFR_MSDC0, "ifr_msdc0", "msdc5hclk", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) GATE_IFR3(CLK_IFR_MSDC1, "ifr_msdc1", "axi_ck", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) GATE_IFR3(CLK_IFR_TRNG, "ifr_trng", "axi_ck", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) GATE_IFR3(CLK_IFR_AUXADC, "ifr_auxadc", "f_f26m_ck", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) GATE_IFR3(CLK_IFR_CCIF1_AP, "ifr_ccif1_ap", "axi_ck", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) GATE_IFR3(CLK_IFR_CCIF1_MD, "ifr_ccif1_md", "axi_ck", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) GATE_IFR3(CLK_IFR_AUXADC_MD, "ifr_auxadc_md", "f_f26m_ck", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) GATE_IFR3(CLK_IFR_AP_DMA, "ifr_ap_dma", "axi_ck", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) GATE_IFR3(CLK_IFR_DEVICE_APC, "ifr_dapc", "axi_ck", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) GATE_IFR3(CLK_IFR_CCIF_AP, "ifr_ccif_ap", "axi_ck", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) GATE_IFR3(CLK_IFR_AUDIO, "ifr_audio", "axi_ck", 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) GATE_IFR3(CLK_IFR_CCIF_MD, "ifr_ccif_md", "axi_ck", 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* INFRA mode 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) GATE_IFR4(CLK_IFR_RG_PWM_FBCLK6, "ifr_pwmfb", "f_f26m_ck", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) GATE_IFR4(CLK_IFR_DISP_PWM, "ifr_disp_pwm", "f_fdisp_pwm_ck", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) GATE_IFR4(CLK_IFR_CLDMA_BCLK, "ifr_cldmabclk", "axi_ck", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) GATE_IFR4(CLK_IFR_AUDIO_26M_BCLK, "ifr_audio26m", "f_f26m_ck", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) GATE_IFR4(CLK_IFR_SPI1, "ifr_spi1", "spi_ck", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) GATE_IFR4(CLK_IFR_I2C4, "ifr_i2c4", "i2c_ck", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) GATE_IFR4(CLK_IFR_SPI2, "ifr_spi2", "spi_ck", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) GATE_IFR4(CLK_IFR_SPI3, "ifr_spi3", "spi_ck", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) GATE_IFR4(CLK_IFR_I2C5, "ifr_i2c5", "i2c_ck", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) GATE_IFR4(CLK_IFR_I2C5_ARBITER, "ifr_i2c5a", "i2c_ck", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) GATE_IFR4(CLK_IFR_I2C5_IMM, "ifr_i2c5_imm", "i2c_ck", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) GATE_IFR4(CLK_IFR_I2C1_ARBITER, "ifr_i2c1a", "i2c_ck", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) GATE_IFR4(CLK_IFR_I2C1_IMM, "ifr_i2c1_imm", "i2c_ck", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) GATE_IFR4(CLK_IFR_I2C2_ARBITER, "ifr_i2c2a", "i2c_ck", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) GATE_IFR4(CLK_IFR_I2C2_IMM, "ifr_i2c2_imm", "i2c_ck", 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) GATE_IFR4(CLK_IFR_SPI4, "ifr_spi4", "spi_ck", 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) GATE_IFR4(CLK_IFR_SPI5, "ifr_spi5", "spi_ck", 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) GATE_IFR4(CLK_IFR_CQ_DMA, "ifr_cq_dma", "axi_ck", 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) GATE_IFR4(CLK_IFR_FAES_FDE, "ifr_faes_fde_ck", "aes_fde_ck", 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* INFRA mode 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) GATE_IFR5(CLK_IFR_MSDC0_SELF, "ifr_msdc0sf", "msdc50_0_ck", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) GATE_IFR5(CLK_IFR_MSDC1_SELF, "ifr_msdc1sf", "msdc50_0_ck", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) GATE_IFR5(CLK_IFR_I2C6, "ifr_i2c6", "i2c_ck", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) GATE_IFR5(CLK_IFR_AP_MSDC0, "ifr_ap_msdc0", "msdc50_0_ck", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) GATE_IFR5(CLK_IFR_MD_MSDC0, "ifr_md_msdc0", "msdc50_0_ck", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) GATE_IFR5(CLK_IFR_MSDC0_SRC, "ifr_msdc0_clk", "msdc50_0_ck", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) GATE_IFR5(CLK_IFR_MSDC1_SRC, "ifr_msdc1_clk", "msdc30_1_ck", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) GATE_IFR5(CLK_IFR_MCU_PM_BCLK, "ifr_mcu_pm_bclk", "axi_ck", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) GATE_IFR5(CLK_IFR_CCIF2_AP, "ifr_ccif2_ap", "axi_ck", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) GATE_IFR5(CLK_IFR_CCIF2_MD, "ifr_ccif2_md", "axi_ck", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) GATE_IFR5(CLK_IFR_CCIF3_AP, "ifr_ccif3_ap", "axi_ck", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) GATE_IFR5(CLK_IFR_CCIF3_MD, "ifr_ccif3_md", "axi_ck", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* additional CCF control for mipi26M race condition(disp/camera) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static const struct mtk_gate_regs apmixed_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .set_ofs = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .clr_ofs = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .sta_ofs = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define GATE_APMIXED(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .regs = &apmixed_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .ops = &mtk_clk_gate_ops_no_setclr_inv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static const struct mtk_gate apmixed_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* AUDIO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) GATE_APMIXED(CLK_APMIXED_SSUSB26M, "apmixed_ssusb26m", "f_f26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) GATE_APMIXED(CLK_APMIXED_APPLL26M, "apmixed_appll26m", "f_f26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m", "f_f26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) GATE_APMIXED(CLK_APMIXED_MDPLLGP26M, "apmixed_mdpll26m", "f_f26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) GATE_APMIXED(CLK_APMIXED_MMSYS_F26M, "apmixed_mmsys26m", "f_f26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) GATE_APMIXED(CLK_APMIXED_UFS26M, "apmixed_ufs26m", "f_f26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m", "f_f26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) GATE_APMIXED(CLK_APMIXED_MEMPLL26M, "apmixed_mempll26m", "f_f26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) "f_f26m_ck", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m", "f_f26m_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define MT6765_PLL_FMAX (3800UL * MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define MT6765_PLL_FMIN (1500UL * MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define CON0_MT6765_RST_BAR BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define PLL_INFO_NULL (0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) _pcwibits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) _tuner_en_bit, _pcw_reg, _pcw_shift, _div_table) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .pwr_reg = _pwr_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .en_mask = _en_mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .rst_bar_mask = CON0_MT6765_RST_BAR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .fmax = MT6765_PLL_FMAX, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .fmin = MT6765_PLL_FMIN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .pcwbits = _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .pcwibits = _pcwibits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .pd_reg = _pd_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .pd_shift = _pd_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .tuner_reg = _tuner_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .tuner_en_reg = _tuner_en_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .tuner_en_bit = _tuner_en_bit, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .pcw_reg = _pcw_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .pcw_shift = _pcw_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .div_table = _div_table, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) _pcwibits, _pd_reg, _pd_shift, _tuner_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) _tuner_en_reg, _tuner_en_bit, _pcw_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) _pcw_shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) _pcwbits, _pcwibits, _pd_reg, _pd_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) _tuner_reg, _tuner_en_reg, _tuner_en_bit, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) _pcw_reg, _pcw_shift, NULL) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static const struct mtk_pll_data plls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) PLL(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x021C, 0x0228, BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) PLL_AO, 22, 8, 0x0220, 24, 0, 0, 0, 0x0220, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) PLL(CLK_APMIXED_ARMPLL, "armpll", 0x020C, 0x0218, BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) PLL_AO, 22, 8, 0x0210, 24, 0, 0, 0, 0x0210, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x022C, 0x0238, BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) PLL_AO, 22, 8, 0x0230, 24, 0, 0, 0, 0x0230, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x023C, 0x0248, BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) (HAVE_RST_BAR | PLL_AO), 22, 8, 0x0240, 24, 0, 0, 0, 0x0240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x024C, 0x0258, BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) 0, 22, 8, 0x0250, 24, 0, 0, 0, 0x0250, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) PLL(CLK_APMIXED_MMPLL, "mmpll", 0x025C, 0x0268, BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) 0, 22, 8, 0x0260, 24, 0, 0, 0, 0x0260, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x026C, 0x0278, BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) HAVE_RST_BAR, 22, 8, 0x0270, 24, 0, 0, 0, 0x0270, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x027C, 0x0288, BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) 0, 22, 8, 0x0280, 24, 0, 0, 0, 0x0280, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) PLL(CLK_APMIXED_APLL1, "apll1", 0x028C, 0x029C, BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) 0, 32, 8, 0x0290, 24, 0x0040, 0x000C, 0, 0x0294, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) PLL(CLK_APMIXED_MPLL, "mpll", 0x02A0, 0x02AC, BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) PLL_AO, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static int clk_mt6765_apmixed_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (IS_ERR(base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) pr_err("%s(): ioremap failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) mtk_clk_register_gates(node, apmixed_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ARRAY_SIZE(apmixed_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) apmixed_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /* MPLL, CCIPLL, MAINPLL set HW mode, TDCLKSQ, CLKSQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) writel(readl(AP_PLL_CON3) & 0xFFFFFFE1, AP_PLL_CON3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) writel(readl(PLLON_CON0) & 0x01041041, PLLON_CON0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) writel(readl(PLLON_CON1) & 0x01041041, PLLON_CON1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static int clk_mt6765_top_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (IS_ERR(base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) pr_err("%s(): ioremap failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) &mt6765_clk_lock, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) cksys_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /* [4]:no need */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) writel(readl(CLK_SCP_CFG_0) | 0x3EF, CLK_SCP_CFG_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /*[1,2,3,8]: no need*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) writel(readl(CLK_SCP_CFG_1) | 0x1, CLK_SCP_CFG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static int clk_mt6765_ifr_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (IS_ERR(base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) pr_err("%s(): ioremap failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) mtk_clk_register_gates(node, ifr_clks, ARRAY_SIZE(ifr_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static const struct of_device_id of_match_clk_mt6765[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .compatible = "mediatek,mt6765-apmixedsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .data = clk_mt6765_apmixed_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .compatible = "mediatek,mt6765-topckgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .data = clk_mt6765_top_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .compatible = "mediatek,mt6765-infracfg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .data = clk_mt6765_ifr_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static int clk_mt6765_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) int (*clk_probe)(struct platform_device *d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) clk_probe = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (!clk_probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) r = clk_probe(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) "could not register clock provider: %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) pdev->name, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static struct platform_driver clk_mt6765_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .probe = clk_mt6765_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .name = "clk-mt6765",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .of_match_table = of_match_clk_mt6765,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static int __init clk_mt6765_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return platform_driver_register(&clk_mt6765_drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) arch_initcall(clk_mt6765_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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