Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Author: Owen Chen <owen.chen@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <dt-bindings/clock/mt6765-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static const struct mtk_gate_regs venc_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	.set_ofs = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	.clr_ofs = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	.sta_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define GATE_VENC(_id, _name, _parent, _shift) {	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		.id = _id,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		.name = _name,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		.parent_name = _parent,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		.regs = &venc_cg_regs,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		.shift = _shift,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		.ops = &mtk_clk_gate_ops_setclr_inv,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static const struct mtk_gate venc_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	GATE_VENC(CLK_VENC_SET0_LARB, "venc_set0_larb", "mm_ck", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	GATE_VENC(CLK_VENC_SET1_VENC, "venc_set1_venc", "mm_ck", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	GATE_VENC(CLK_VENC_SET2_JPGENC, "jpgenc", "mm_ck", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	GATE_VENC(CLK_VENC_SET3_VDEC, "venc_set3_vdec", "mm_ck", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int clk_mt6765_vcodec_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	mtk_clk_register_gates(node, venc_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 			       ARRAY_SIZE(venc_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		       __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static const struct of_device_id of_match_clk_mt6765_vcodec[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	{ .compatible = "mediatek,mt6765-vcodecsys", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static struct platform_driver clk_mt6765_vcodec_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	.probe = clk_mt6765_vcodec_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		.name = "clk-mt6765-vcodec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 		.of_match_table = of_match_clk_mt6765_vcodec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) builtin_platform_driver(clk_mt6765_vcodec_drv);