^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Owen Chen <owen.chen@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <dt-bindings/clock/mt6765-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static const struct mtk_gate_regs mm_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) .set_ofs = 0x104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) .clr_ofs = 0x108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) .sta_ofs = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define GATE_MM(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .regs = &mm_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static const struct mtk_gate mm_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* MM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) GATE_MM(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_ck", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) GATE_MM(CLK_MM_MDP_CCORR0, "mm_mdp_ccorr0", "mm_ck", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) GATE_MM(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_ck", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) GATE_MM(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_ck", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) GATE_MM(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_ck", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) GATE_MM(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_ck", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) GATE_MM(CLK_MM_MDP_WDMA0, "mm_mdp_wdma0", "mm_ck", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) GATE_MM(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_ck", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) GATE_MM(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_ck", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) GATE_MM(CLK_MM_DISP_RSZ0, "mm_disp_rsz0", "mm_ck", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) GATE_MM(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_ck", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) GATE_MM(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_ck", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) GATE_MM(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_ck", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) GATE_MM(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "mm_ck", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) GATE_MM(CLK_MM_DISP_AAL0, "mm_disp_aal0", "mm_ck", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) GATE_MM(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "mm_ck", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) GATE_MM(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "mm_ck", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) GATE_MM(CLK_MM_DSI0, "mm_dsi0", "mm_ck", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) GATE_MM(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_ck", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) GATE_MM(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_ck", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) GATE_MM(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_ck", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) GATE_MM(CLK_MM_SMI_COMM0, "mm_smi_comm0", "mm_ck", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) GATE_MM(CLK_MM_SMI_COMM1, "mm_smi_comm1", "mm_ck", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) GATE_MM(CLK_MM_CAM_MDP, "mm_cam_mdp_ck", "mm_ck", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) GATE_MM(CLK_MM_SMI_IMG, "mm_smi_img_ck", "mm_ck", 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) GATE_MM(CLK_MM_SMI_CAM, "mm_smi_cam_ck", "mm_ck", 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) GATE_MM(CLK_MM_IMG_DL_RELAY, "mm_img_dl_relay", "mm_ck", 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) GATE_MM(CLK_MM_IMG_DL_ASYNC_TOP, "mm_imgdl_async", "mm_ck", 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) GATE_MM(CLK_MM_DIG_DSI, "mm_dig_dsi_ck", "mm_ck", 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) GATE_MM(CLK_MM_F26M_HRTWT, "mm_hrtwt", "f_f26m_ck", 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static int clk_mt6765_mm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const struct of_device_id of_match_clk_mt6765_mm[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { .compatible = "mediatek,mt6765-mmsys", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static struct platform_driver clk_mt6765_mm_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .probe = clk_mt6765_mm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .name = "clk-mt6765-mm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .of_match_table = of_match_clk_mt6765_mm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) builtin_platform_driver(clk_mt6765_mm_drv);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags