^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Owen Chen <owen.chen@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <dt-bindings/clock/mt6765-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static const struct mtk_gate_regs audio0_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) .set_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) .clr_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) .sta_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static const struct mtk_gate_regs audio1_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .set_ofs = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .clr_ofs = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .sta_ofs = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GATE_AUDIO0(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .regs = &audio0_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .ops = &mtk_clk_gate_ops_no_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GATE_AUDIO1(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .regs = &audio1_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .ops = &mtk_clk_gate_ops_no_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static const struct mtk_gate audio_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* AUDIO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) GATE_AUDIO0(CLK_AUDIO_AFE, "aud_afe", "audio_ck", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) GATE_AUDIO0(CLK_AUDIO_22M, "aud_22m", "aud_engen1_ck", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) GATE_AUDIO0(CLK_AUDIO_APLL_TUNER, "aud_apll_tuner",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) "aud_engen1_ck", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) GATE_AUDIO0(CLK_AUDIO_ADC, "aud_adc", "audio_ck", 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) GATE_AUDIO0(CLK_AUDIO_DAC, "aud_dac", "audio_ck", 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) GATE_AUDIO0(CLK_AUDIO_DAC_PREDIS, "aud_dac_predis",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) "audio_ck", 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) GATE_AUDIO0(CLK_AUDIO_TML, "aud_tml", "audio_ck", 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* AUDIO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) GATE_AUDIO1(CLK_AUDIO_I2S1_BCLK, "aud_i2s1_bclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) "audio_ck", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) GATE_AUDIO1(CLK_AUDIO_I2S2_BCLK, "aud_i2s2_bclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) "audio_ck", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) GATE_AUDIO1(CLK_AUDIO_I2S3_BCLK, "aud_i2s3_bclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "audio_ck", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) GATE_AUDIO1(CLK_AUDIO_I2S4_BCLK, "aud_i2s4_bclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) "audio_ck", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int clk_mt6765_audio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) mtk_clk_register_gates(node, audio_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ARRAY_SIZE(audio_clks), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static const struct of_device_id of_match_clk_mt6765_audio[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { .compatible = "mediatek,mt6765-audsys", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static struct platform_driver clk_mt6765_audio_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .probe = clk_mt6765_audio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .name = "clk-mt6765-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .of_match_table = of_match_clk_mt6765_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) builtin_platform_driver(clk_mt6765_audio_drv);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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