^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2017 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Weiyi Lu <weiyi.lu@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <dt-bindings/clock/mt2712-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static DEFINE_SPINLOCK(mt2712_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static const struct mtk_fixed_clk top_fixed_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) FIXED_CLK(CLK_TOP_VPLL3_DPIX, "vpll3_dpix", NULL, 200000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", NULL, 200000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) FIXED_CLK(CLK_TOP_LTEPLL_FS26M, "ltepll_fs26m", NULL, 26000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 350000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) FIXED_CLK(CLK_TOP_DSI0_LNTC, "dsi0_lntc", NULL, 143000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) FIXED_CLK(CLK_TOP_DSI1_LNTC, "dsi1_lntc", NULL, 143000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) FIXED_CLK(CLK_TOP_LVDSTX3_CLKDIG_CTS, "lvdstx3", NULL, 140000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx", NULL, 140000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) FIXED_CLK(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", NULL, 32768),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) FIXED_CLK(CLK_TOP_CLKRTC_INT, "clkrtc_int", NULL, 32747),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) FIXED_CLK(CLK_TOP_CSI0, "csi0", NULL, 26000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) FIXED_CLK(CLK_TOP_CVBSPLL, "cvbspll", NULL, 108000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static const struct mtk_fixed_factor top_early_divs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) FACTOR(CLK_TOP_SYS_26M, "sys_26m", "clk26m", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "sys_26m", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static const struct mtk_fixed_factor top_divs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) FACTOR(CLK_TOP_ARMCA35PLL, "armca35pll_ck", "armca35pll", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) FACTOR(CLK_TOP_ARMCA35PLL_600M, "armca35pll_600m", "armca35pll_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) FACTOR(CLK_TOP_ARMCA35PLL_400M, "armca35pll_400m", "armca35pll_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) FACTOR(CLK_TOP_ARMCA72PLL, "armca72pll_ck", "armca72pll", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "syspll_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "syspll_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "syspll_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 52),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) FACTOR(CLK_TOP_UNIVPLL_D104, "univpll_d104", "univpll_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 104),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) FACTOR(CLK_TOP_UNIVPLL_D208, "univpll_d208", "univpll_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 208),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) FACTOR(CLK_TOP_F_MP0_PLL1, "f_mp0_pll1_ck", "univpll_d2", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) FACTOR(CLK_TOP_F_MP0_PLL2, "f_mp0_pll2_ck", "univpll1_d2", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) FACTOR(CLK_TOP_F_BIG_PLL1, "f_big_pll1_ck", "univpll_d2", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) FACTOR(CLK_TOP_F_BIG_PLL2, "f_big_pll2_ck", "univpll1_d2", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) FACTOR(CLK_TOP_F_BUS_PLL1, "f_bus_pll1_ck", "univpll_d2", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) FACTOR(CLK_TOP_F_BUS_PLL2, "f_bus_pll2_ck", "univpll1_d2", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) FACTOR(CLK_TOP_APLL1_D16, "apll1_d16", "apll1_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) FACTOR(CLK_TOP_APLL2_D16, "apll2_d16", "apll2_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) FACTOR(CLK_TOP_LVDSPLL2, "lvdspll2_ck", "lvdspll2", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) FACTOR(CLK_TOP_LVDSPLL2_D2, "lvdspll2_d2", "lvdspll2_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) FACTOR(CLK_TOP_LVDSPLL2_D4, "lvdspll2_d4", "lvdspll2_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) FACTOR(CLK_TOP_LVDSPLL2_D8, "lvdspll2_d8", "lvdspll2_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) FACTOR(CLK_TOP_ETHERPLL_125M, "etherpll_125m", "etherpll", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) FACTOR(CLK_TOP_ETHERPLL_50M, "etherpll_50m", "etherpll", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) FACTOR(CLK_TOP_CVBS, "cvbs", "cvbspll", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) FACTOR(CLK_TOP_CVBS_D2, "cvbs_d2", "cvbs", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) FACTOR(CLK_TOP_VCODECPLL_D2, "vcodecpll_d2", "vcodecpll_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) FACTOR(CLK_TOP_TVDPLL_429M, "tvdpll_429m", "tvdpll", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) FACTOR(CLK_TOP_TVDPLL_429M_D2, "tvdpll_429m_d2", "tvdpll_429m", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) FACTOR(CLK_TOP_TVDPLL_429M_D4, "tvdpll_429m_d4", "tvdpll_429m", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) FACTOR(CLK_TOP_D2A_ULCLK_6P5M, "d2a_ulclk_6p5m", "clk26m", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2_ck", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const char * const axi_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) "syspll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) "syspll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "msdcpll2_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const char * const mem_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) "dmpll_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const char * const mm_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) "vencpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) "syspll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) "syspll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) "syspll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) "univpll2_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const char * const pwm_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) "univpll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) "univpll1_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const char * const vdec_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) "vcodecpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) "tvdpll_429m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) "vencpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) "syspll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) "mmpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) "syspll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) "tvdpll_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const char * const venc_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) "mmpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) "tvdpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) "vcodecpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) "syspll3_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const char * const mfg_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) "mmpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) "syspll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) "syspll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) "univpll2_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const char * const camtg_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) "univpll_d52",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) "univpll_d208",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) "univpll_d104",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) "clk26m_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) "univpll_d26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) "univpll2_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "syspll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "syspll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) "univpll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "univpll2_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static const char * const uart_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) "univpll2_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const char * const spi_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) "univpll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) "univpll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) "univpll1_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static const char * const usb20_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) "univpll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) "univpll3_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static const char * const usb30_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) "univpll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) "univpll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) "univpll2_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const char * const msdc50_0_h_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) "syspll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) "syspll4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) "univpll1_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const char * const msdc50_0_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) "msdcpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) "msdcpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) "univpll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) "syspll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) "msdcpll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) "vencpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) "msdcpll2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) "msdcpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) "msdcpll2_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static const char * const msdc30_1_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) "msdcpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) "univpll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) "syspll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) "univpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) "vencpll_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const char * const msdc30_3_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) "msdcpll2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) "msdcpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) "msdcpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) "univpll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) "syspll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) "syspll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) "univpll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) "vencpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) "msdcpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) "msdcpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) "msdcpll_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static const char * const audio_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) "syspll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) "syspll4_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) "syspll1_d16"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static const char * const aud_intbus_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) "syspll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) "syspll4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) "univpll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) "univpll2_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) "syspll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) "syspll3_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static const char * const pmicspi_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) "syspll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) "syspll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) "syspll1_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) "univpll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) "univpll_d26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) "syspll3_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static const char * const dpilvds1_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) "lvdspll2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) "lvdspll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) "lvdspll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) "lvdspll2_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) "clkfpc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static const char * const atb_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) "syspll_d5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static const char * const nr_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) "univpll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) "syspll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) "syspll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) "univpll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) "univpll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) "syspll_d5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static const char * const nfi2x_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) "syspll4_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) "univpll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) "univpll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) "syspll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) "univpll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) "syspll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) "syspll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) "syspll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) "syspll1_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static const char * const irda_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) "syspll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) "univpll2_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static const char * const cci400_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) "vencpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) "armca35pll_600m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) "armca35pll_400m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) "univpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) "syspll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) "msdcpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) "univpll_d3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static const char * const aud_1_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) "apll1_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) "univpll2_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static const char * const aud_2_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) "apll2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) "univpll2_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static const char * const mem_mfg_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) "mmpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) "univpll_d3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static const char * const axi_mfg_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) "axi_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) "univpll_d5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static const char * const scam_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) "syspll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) "syspll2_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static const char * const nfiecc_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) "nfi2x_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) "syspll_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) "syspll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) "syspll1_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static const char * const pe2_mac_p0_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) "syspll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) "syspll4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) "syspll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) "syspll3_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static const char * const dpilvds_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) "lvdspll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) "lvdspll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) "lvdspll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) "lvdspll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) "clkfpc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static const char * const hdcp_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) "syspll4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) "syspll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) "univpll2_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static const char * const hdcp_24m_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) "univpll_d26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) "univpll_d52",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) "univpll2_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static const char * const rtc_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) "clkrtc_int",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) "clkrtc_ext",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) "univpll3_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static const char * const spinor_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) "clk26m_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) "syspll4_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) "univpll2_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) "univpll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) "syspll4_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) "syspll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) "etherpll_125m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) "syspll1_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static const char * const apll_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) "apll1_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) "apll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) "apll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) "apll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) "apll1_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) "apll2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) "apll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) "apll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) "apll2_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) "apll2_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) "clk26m"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static const char * const a1sys_hp_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) "apll1_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) "apll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) "apll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) "apll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) "apll1_d3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static const char * const a2sys_hp_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) "apll2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) "apll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) "apll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) "apll2_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) "apll2_d3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static const char * const asm_l_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) "syspll_d5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static const char * const i2so1_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) "apll1_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) "apll2_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static const char * const ether_125m_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) "etherpll_125m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) "univpll3_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static const char * const ether_50m_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) "etherpll_50m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) "apll1_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) "univpll3_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static const char * const jpgdec_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) "tvdpll_429m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) "vencpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) "syspll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) "vcodecpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) "armca35pll_400m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) "tvdpll_429m_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) "tvdpll_429m_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static const char * const spislv_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) "univpll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) "univpll2_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) "univpll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) "univpll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) "univpll_d5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static const char * const ether_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) "etherpll_50m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) "univpll_d26"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static const char * const di_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) "tvdpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) "tvdpll_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) "tvdpll_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) "vencpll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) "vencpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) "cvbs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) "cvbs_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static const char * const tvd_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) "cvbs_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) "univpll2_d8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static const char * const i2c_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) "univpll_d26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) "univpll2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) "univpll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) "univpll1_d4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static const char * const msdc0p_aes_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) "syspll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) "vcodecpll_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static const char * const cmsys_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) "univpll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) "syspll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) "syspll2_d2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static const char * const gcpu_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) "syspll_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) "syspll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) "univpll1_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) "univpll_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) "univpll3_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) "univpll_d3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static const char * const aud_apll1_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) "apll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) "clkaud_ext_i_1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static const char * const aud_apll2_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) "apll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) "clkaud_ext_i_2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static const char * const apll1_ref_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) "clkaud_ext_i_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) "clkaud_ext_i_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) "clki2si0_mck_i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) "clki2si1_mck_i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) "clki2si2_mck_i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) "clktdmin_mclk_i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) "clki2si2_mck_i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) "clktdmin_mclk_i"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static const char * const audull_vtx_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) "d2a_ulclk_6p5m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) "clkaud_ext_i_0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static struct mtk_composite top_muxes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* CLK_CFG_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 7, CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) 15, CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) MUX_GATE(CLK_TOP_MM_SEL, "mm_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) mm_parents, 0x040, 24, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* CLK_CFG_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) pwm_parents, 0x050, 0, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) vdec_parents, 0x050, 8, 4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) venc_parents, 0x050, 16, 4, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) mfg_parents, 0x050, 24, 4, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* CLK_CFG_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) camtg_parents, 0x060, 0, 4, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) MUX_GATE(CLK_TOP_UART_SEL, "uart_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) uart_parents, 0x060, 8, 1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) spi_parents, 0x060, 16, 3, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) usb20_parents, 0x060, 24, 2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* CLK_CFG_3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) usb30_parents, 0x070, 0, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) MUX_GATE(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc50_0_h_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) msdc50_0_h_parents, 0x070, 8, 3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) msdc50_0_parents, 0x070, 16, 4, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) msdc30_1_parents, 0x070, 24, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /* CLK_CFG_4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) msdc30_1_parents, 0x080, 0, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) msdc30_3_parents, 0x080, 8, 4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) audio_parents, 0x080, 16, 2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) aud_intbus_parents, 0x080, 24, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* CLK_CFG_5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) pmicspi_parents, 0x090, 0, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) MUX_GATE(CLK_TOP_DPILVDS1_SEL, "dpilvds1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) dpilvds1_parents, 0x090, 8, 3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) atb_parents, 0x090, 16, 2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) MUX_GATE(CLK_TOP_NR_SEL, "nr_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) nr_parents, 0x090, 24, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* CLK_CFG_6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) nfi2x_parents, 0x0a0, 0, 4, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) irda_parents, 0x0a0, 8, 2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) cci400_parents, 0x0a0, 16, 3, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) aud_1_parents, 0x0a0, 24, 2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* CLK_CFG_7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) aud_2_parents, 0x0b0, 0, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) MUX_GATE(CLK_TOP_MEM_MFG_IN_AS_SEL, "mem_mfg_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) mem_mfg_parents, 0x0b0, 8, 2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) MUX_GATE(CLK_TOP_AXI_MFG_IN_AS_SEL, "axi_mfg_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) axi_mfg_parents, 0x0b0, 16, 2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) scam_parents, 0x0b0, 24, 2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /* CLK_CFG_8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) MUX_GATE(CLK_TOP_NFIECC_SEL, "nfiecc_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) nfiecc_parents, 0x0c0, 0, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) MUX_GATE(CLK_TOP_PE2_MAC_P0_SEL, "pe2_mac_p0_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) pe2_mac_p0_parents, 0x0c0, 8, 3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) MUX_GATE(CLK_TOP_PE2_MAC_P1_SEL, "pe2_mac_p1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) pe2_mac_p0_parents, 0x0c0, 16, 3, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) dpilvds_parents, 0x0c0, 24, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* CLK_CFG_9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) MUX_GATE(CLK_TOP_MSDC50_3_HCLK_SEL, "msdc50_3_h_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) msdc50_0_h_parents, 0x0d0, 0, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) hdcp_parents, 0x0d0, 8, 2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) hdcp_24m_parents, 0x0d0, 16, 2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x0d0, 24, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) 31, CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* CLK_CFG_10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) MUX_GATE(CLK_TOP_SPINOR_SEL, "spinor_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) spinor_parents, 0x500, 0, 4, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) apll_parents, 0x500, 8, 4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) MUX_GATE(CLK_TOP_APLL2_SEL, "apll2_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) apll_parents, 0x500, 16, 4, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) a1sys_hp_parents, 0x500, 24, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* CLK_CFG_11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) a2sys_hp_parents, 0x510, 0, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) asm_l_parents, 0x510, 8, 2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) asm_l_parents, 0x510, 16, 2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) asm_l_parents, 0x510, 24, 2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /* CLK_CFG_12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) MUX_GATE(CLK_TOP_I2SO1_SEL, "i2so1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) i2so1_parents, 0x520, 0, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) MUX_GATE(CLK_TOP_I2SO2_SEL, "i2so2_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) i2so1_parents, 0x520, 8, 2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) MUX_GATE(CLK_TOP_I2SO3_SEL, "i2so3_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) i2so1_parents, 0x520, 16, 2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) MUX_GATE(CLK_TOP_TDMO0_SEL, "tdmo0_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) i2so1_parents, 0x520, 24, 2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) /* CLK_CFG_13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) MUX_GATE(CLK_TOP_TDMO1_SEL, "tdmo1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) i2so1_parents, 0x530, 0, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) MUX_GATE(CLK_TOP_I2SI1_SEL, "i2si1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) i2so1_parents, 0x530, 8, 2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) MUX_GATE(CLK_TOP_I2SI2_SEL, "i2si2_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) i2so1_parents, 0x530, 16, 2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) MUX_GATE(CLK_TOP_I2SI3_SEL, "i2si3_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) i2so1_parents, 0x530, 24, 2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /* CLK_CFG_14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) MUX_GATE(CLK_TOP_ETHER_125M_SEL, "ether_125m_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ether_125m_parents, 0x540, 0, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) MUX_GATE(CLK_TOP_ETHER_50M_SEL, "ether_50m_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) ether_50m_parents, 0x540, 8, 2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) MUX_GATE(CLK_TOP_JPGDEC_SEL, "jpgdec_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) jpgdec_parents, 0x540, 16, 4, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) MUX_GATE(CLK_TOP_SPISLV_SEL, "spislv_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) spislv_parents, 0x540, 24, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* CLK_CFG_15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) MUX_GATE(CLK_TOP_ETHER_50M_RMII_SEL, "ether_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) ether_parents, 0x550, 0, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) MUX_GATE(CLK_TOP_CAM2TG_SEL, "cam2tg_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) camtg_parents, 0x550, 8, 4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) MUX_GATE(CLK_TOP_DI_SEL, "di_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) di_parents, 0x550, 16, 3, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) MUX_GATE(CLK_TOP_TVD_SEL, "tvd_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) tvd_parents, 0x550, 24, 2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) /* CLK_CFG_16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) MUX_GATE(CLK_TOP_I2C_SEL, "i2c_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) i2c_parents, 0x560, 0, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) MUX_GATE(CLK_TOP_PWM_INFRA_SEL, "pwm_infra_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) pwm_parents, 0x560, 8, 2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) MUX_GATE(CLK_TOP_MSDC0P_AES_SEL, "msdc0p_aes_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) msdc0p_aes_parents, 0x560, 16, 2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) cmsys_parents, 0x560, 24, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /* CLK_CFG_17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) gcpu_parents, 0x570, 0, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* CLK_AUDDIV_4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) MUX(CLK_TOP_AUD_APLL1_SEL, "aud_apll1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) aud_apll1_parents, 0x134, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) MUX(CLK_TOP_AUD_APLL2_SEL, "aud_apll2_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) aud_apll2_parents, 0x134, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) MUX(CLK_TOP_DA_AUDULL_VTX_6P5M_SEL, "audull_vtx_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) audull_vtx_parents, 0x134, 31, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) MUX(CLK_TOP_APLL1_REF_SEL, "apll1_ref_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) apll1_ref_parents, 0x134, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) MUX(CLK_TOP_APLL2_REF_SEL, "apll2_ref_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) apll1_ref_parents, 0x134, 7, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) static const char * const mcu_mp0_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) "armca35pll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) "f_mp0_pll1_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) "f_mp0_pll2_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static const char * const mcu_mp2_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) "armca72pll_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) "f_big_pll1_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) "f_big_pll2_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static const char * const mcu_bus_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) "clk26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) "cci400_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) "f_bus_pll1_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) "f_bus_pll2_ck"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static struct mtk_composite mcu_muxes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /* mp0_pll_divider_cfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) MUX_GATE_FLAGS(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) 9, 2, -1, CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /* mp2_pll_divider_cfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) MUX_GATE_FLAGS(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) 9, 2, -1, CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* bus_pll_divider_cfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) 9, 2, -1, CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static const struct mtk_clk_divider top_adj_divs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) DIV_ADJ(CLK_TOP_APLL_DIV0, "apll_div0", "i2so1_sel", 0x124, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) DIV_ADJ(CLK_TOP_APLL_DIV1, "apll_div1", "i2so2_sel", 0x124, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) DIV_ADJ(CLK_TOP_APLL_DIV2, "apll_div2", "i2so3_sel", 0x124, 16, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) DIV_ADJ(CLK_TOP_APLL_DIV3, "apll_div3", "tdmo0_sel", 0x124, 24, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) DIV_ADJ(CLK_TOP_APLL_DIV4, "apll_div4", "tdmo1_sel", 0x128, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) DIV_ADJ(CLK_TOP_APLL_DIV5, "apll_div5", "i2si1_sel", 0x128, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) DIV_ADJ(CLK_TOP_APLL_DIV6, "apll_div6", "i2si2_sel", 0x128, 16, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) DIV_ADJ(CLK_TOP_APLL_DIV7, "apll_div7", "i2si3_sel", 0x128, 24, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static const struct mtk_gate_regs top0_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .set_ofs = 0x120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .clr_ofs = 0x120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .sta_ofs = 0x120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static const struct mtk_gate_regs top1_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .set_ofs = 0x424,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .clr_ofs = 0x424,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .sta_ofs = 0x424,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define GATE_TOP0(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .regs = &top0_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .ops = &mtk_clk_gate_ops_no_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define GATE_TOP1(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .regs = &top1_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .ops = &mtk_clk_gate_ops_no_setclr_inv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static const struct mtk_gate top_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /* TOP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) GATE_TOP0(CLK_TOP_APLL_DIV_PDN0, "apll_div_pdn0", "i2so1_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) GATE_TOP0(CLK_TOP_APLL_DIV_PDN1, "apll_div_pdn1", "i2so2_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) GATE_TOP0(CLK_TOP_APLL_DIV_PDN2, "apll_div_pdn2", "i2so3_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) GATE_TOP0(CLK_TOP_APLL_DIV_PDN3, "apll_div_pdn3", "tdmo0_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) GATE_TOP0(CLK_TOP_APLL_DIV_PDN4, "apll_div_pdn4", "tdmo1_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) GATE_TOP0(CLK_TOP_APLL_DIV_PDN5, "apll_div_pdn5", "i2si1_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) GATE_TOP0(CLK_TOP_APLL_DIV_PDN6, "apll_div_pdn6", "i2si2_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) GATE_TOP0(CLK_TOP_APLL_DIV_PDN7, "apll_div_pdn7", "i2si3_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) /* TOP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) GATE_TOP1(CLK_TOP_NFI2X_EN, "nfi2x_en", "nfi2x_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) GATE_TOP1(CLK_TOP_NFIECC_EN, "nfiecc_en", "nfiecc_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) GATE_TOP1(CLK_TOP_NFI1X_CK_EN, "nfi1x_ck_en", "nfi2x_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) static const struct mtk_gate_regs infra_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .set_ofs = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .clr_ofs = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .sta_ofs = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) #define GATE_INFRA(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .regs = &infra_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static const struct mtk_gate infra_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) GATE_INFRA(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) GATE_INFRA(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) GATE_INFRA(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) GATE_INFRA(CLK_INFRA_KP, "infra_kp", "axi_sel", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) GATE_INFRA(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "spi_sel", 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) GATE_INFRA(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "spislv_sel", 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) GATE_INFRA(CLK_INFRA_AO_UART5, "infra_ao_uart5", "axi_sel", 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static const struct mtk_gate_regs peri0_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .set_ofs = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .clr_ofs = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .sta_ofs = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) static const struct mtk_gate_regs peri1_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .set_ofs = 0xc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .clr_ofs = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .sta_ofs = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) static const struct mtk_gate_regs peri2_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .set_ofs = 0x42c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .clr_ofs = 0x42c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .sta_ofs = 0x42c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #define GATE_PERI0(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .regs = &peri0_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #define GATE_PERI1(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .regs = &peri1_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) #define GATE_PERI2(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .regs = &peri2_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .ops = &mtk_clk_gate_ops_no_setclr_inv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static const struct mtk_gate peri_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /* PERI0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) GATE_PERI0(CLK_PERI_NFI, "per_nfi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) "axi_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) GATE_PERI0(CLK_PERI_THERM, "per_therm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) "axi_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) GATE_PERI0(CLK_PERI_PWM0, "per_pwm0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) "pwm_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) GATE_PERI0(CLK_PERI_PWM1, "per_pwm1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) "pwm_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) GATE_PERI0(CLK_PERI_PWM2, "per_pwm2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) "pwm_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) GATE_PERI0(CLK_PERI_PWM3, "per_pwm3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) "pwm_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) GATE_PERI0(CLK_PERI_PWM4, "per_pwm4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) "pwm_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) GATE_PERI0(CLK_PERI_PWM5, "per_pwm5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) "pwm_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) GATE_PERI0(CLK_PERI_PWM6, "per_pwm6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) "pwm_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) GATE_PERI0(CLK_PERI_PWM7, "per_pwm7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) "pwm_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) GATE_PERI0(CLK_PERI_PWM, "per_pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) "pwm_sel", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) GATE_PERI0(CLK_PERI_AP_DMA, "per_ap_dma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) "axi_sel", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) GATE_PERI0(CLK_PERI_MSDC30_0, "per_msdc30_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) "msdc50_0_sel", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) GATE_PERI0(CLK_PERI_MSDC30_1, "per_msdc30_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) "msdc30_1_sel", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) GATE_PERI0(CLK_PERI_MSDC30_2, "per_msdc30_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) "msdc30_2_sel", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) GATE_PERI0(CLK_PERI_MSDC30_3, "per_msdc30_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) "msdc30_3_sel", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) GATE_PERI0(CLK_PERI_UART0, "per_uart0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) "uart_sel", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) GATE_PERI0(CLK_PERI_UART1, "per_uart1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) "uart_sel", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) GATE_PERI0(CLK_PERI_UART2, "per_uart2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) "uart_sel", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) GATE_PERI0(CLK_PERI_UART3, "per_uart3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) "uart_sel", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) GATE_PERI0(CLK_PERI_I2C0, "per_i2c0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) "axi_sel", 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) GATE_PERI0(CLK_PERI_I2C1, "per_i2c1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) "axi_sel", 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) GATE_PERI0(CLK_PERI_I2C2, "per_i2c2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) "axi_sel", 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) GATE_PERI0(CLK_PERI_I2C3, "per_i2c3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) "axi_sel", 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) GATE_PERI0(CLK_PERI_I2C4, "per_i2c4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) "axi_sel", 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) GATE_PERI0(CLK_PERI_AUXADC, "per_auxadc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) "ltepll_fs26m", 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) GATE_PERI0(CLK_PERI_SPI0, "per_spi0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) "spi_sel", 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /* PERI1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) GATE_PERI1(CLK_PERI_SPI, "per_spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) "spinor_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) GATE_PERI1(CLK_PERI_I2C5, "per_i2c5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) "axi_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) GATE_PERI1(CLK_PERI_SPI2, "per_spi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) "spi_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) GATE_PERI1(CLK_PERI_SPI3, "per_spi3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) "spi_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) GATE_PERI1(CLK_PERI_SPI5, "per_spi5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) "spi_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) GATE_PERI1(CLK_PERI_UART4, "per_uart4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) "uart_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) GATE_PERI1(CLK_PERI_SFLASH, "per_sflash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) "uart_sel", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) GATE_PERI1(CLK_PERI_GMAC, "per_gmac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) "uart_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) GATE_PERI1(CLK_PERI_PCIE0, "per_pcie0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) "uart_sel", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) GATE_PERI1(CLK_PERI_PCIE1, "per_pcie1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) "uart_sel", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) GATE_PERI1(CLK_PERI_GMAC_PCLK, "per_gmac_pclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) "uart_sel", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) /* PERI2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) GATE_PERI2(CLK_PERI_MSDC50_0_EN, "per_msdc50_0_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) "msdc50_0_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) GATE_PERI2(CLK_PERI_MSDC30_1_EN, "per_msdc30_1_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) "msdc30_1_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) GATE_PERI2(CLK_PERI_MSDC30_2_EN, "per_msdc30_2_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) "msdc30_2_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) GATE_PERI2(CLK_PERI_MSDC30_3_EN, "per_msdc30_3_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) "msdc30_3_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) GATE_PERI2(CLK_PERI_MSDC50_0_HCLK_EN, "per_msdc50_0_h",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) "msdc50_0_h_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) GATE_PERI2(CLK_PERI_MSDC50_3_HCLK_EN, "per_msdc50_3_h",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) "msdc50_3_h_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) GATE_PERI2(CLK_PERI_MSDC30_0_QTR_EN, "per_msdc30_0_q",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) "axi_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) GATE_PERI2(CLK_PERI_MSDC30_3_QTR_EN, "per_msdc30_3_q",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) "mem_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define MT2712_PLL_FMAX (3000UL * MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #define CON0_MT2712_RST_BAR BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) _tuner_en_bit, _pcw_reg, _pcw_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) _div_table) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .pwr_reg = _pwr_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .en_mask = _en_mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .rst_bar_mask = CON0_MT2712_RST_BAR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .fmax = MT2712_PLL_FMAX, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .pcwbits = _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .pd_reg = _pd_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .pd_shift = _pd_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .tuner_reg = _tuner_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .tuner_en_reg = _tuner_en_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .tuner_en_bit = _tuner_en_bit, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .pcw_reg = _pcw_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .pcw_shift = _pcw_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .div_table = _div_table, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) _tuner_en_bit, _pcw_reg, _pcw_shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) _pcwbits, _pd_reg, _pd_shift, _tuner_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) _tuner_en_reg, _tuner_en_bit, _pcw_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) _pcw_shift, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) static const struct mtk_pll_div_table armca35pll_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) { .div = 0, .freq = MT2712_PLL_FMAX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) { .div = 1, .freq = 1202500000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) { .div = 2, .freq = 500500000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) { .div = 3, .freq = 315250000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) { .div = 4, .freq = 157625000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) { } /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) static const struct mtk_pll_div_table armca72pll_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) { .div = 0, .freq = MT2712_PLL_FMAX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) { .div = 1, .freq = 994500000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) { .div = 2, .freq = 520000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) { .div = 3, .freq = 315250000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) { .div = 4, .freq = 157625000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) { } /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) static const struct mtk_pll_div_table mmpll_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) { .div = 0, .freq = MT2712_PLL_FMAX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) { .div = 1, .freq = 1001000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) { .div = 2, .freq = 601250000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) { .div = 3, .freq = 250250000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) { .div = 4, .freq = 125125000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) { } /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) static const struct mtk_pll_data plls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) 0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) 0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) 0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) 0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) 0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) 0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) 0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) 0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) 0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) 0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) mmpll_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) armca35pll_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) 0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) armca72pll_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) 0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) if (r != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) static struct clk_onecell_data *top_clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) static void clk_mt2712_top_init_early(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) int r, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) if (!top_clk_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) for (i = 0; i < CLK_TOP_NR_CLK; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) top_clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) CLK_OF_DECLARE_DRIVER(mt2712_topckgen, "mediatek,mt2712-topckgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) clk_mt2712_top_init_early);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) static int clk_mt2712_top_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) int r, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) if (IS_ERR(base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) pr_err("%s(): ioremap failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) if (!top_clk_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) for (i = 0; i < CLK_TOP_NR_CLK; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (top_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) top_clk_data->clks[i] = ERR_PTR(-ENOENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) top_clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) top_clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) &mt2712_clk_lock, top_clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) &mt2712_clk_lock, top_clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) top_clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (r != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) static int clk_mt2712_infra_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) if (r != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) mtk_register_reset_controller(node, 2, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) static int clk_mt2712_peri_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (r != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) mtk_register_reset_controller(node, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) static int clk_mt2712_mcu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (IS_ERR(base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) pr_err("%s(): ioremap failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) &mt2712_clk_lock, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) if (r != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) static const struct of_device_id of_match_clk_mt2712[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .compatible = "mediatek,mt2712-apmixedsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .data = clk_mt2712_apmixed_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) .compatible = "mediatek,mt2712-topckgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .data = clk_mt2712_top_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .compatible = "mediatek,mt2712-infracfg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .data = clk_mt2712_infra_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .compatible = "mediatek,mt2712-pericfg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .data = clk_mt2712_peri_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .compatible = "mediatek,mt2712-mcucfg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .data = clk_mt2712_mcu_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) static int clk_mt2712_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) int (*clk_probe)(struct platform_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) clk_probe = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) if (!clk_probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) r = clk_probe(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) if (r != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) "could not register clock provider: %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) pdev->name, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) static struct platform_driver clk_mt2712_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .probe = clk_mt2712_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .name = "clk-mt2712",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .of_match_table = of_match_clk_mt2712,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) static int __init clk_mt2712_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) return platform_driver_register(&clk_mt2712_drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) arch_initcall(clk_mt2712_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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