Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2017 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Author: Weiyi Lu <weiyi.lu@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <dt-bindings/clock/mt2712-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static const struct mtk_gate_regs vdec0_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	.set_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	.clr_ofs = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	.sta_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static const struct mtk_gate_regs vdec1_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	.set_ofs = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	.clr_ofs = 0xc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	.sta_ofs = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GATE_VDEC0(_id, _name, _parent, _shift) {	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		.id = _id,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		.name = _name,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		.parent_name = _parent,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		.regs = &vdec0_cg_regs,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		.shift = _shift,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		.ops = &mtk_clk_gate_ops_setclr_inv,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GATE_VDEC1(_id, _name, _parent, _shift) {	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		.id = _id,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		.name = _name,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		.parent_name = _parent,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		.regs = &vdec1_cg_regs,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		.shift = _shift,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		.ops = &mtk_clk_gate_ops_setclr_inv,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static const struct mtk_gate vdec_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	/* VDEC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	/* VDEC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	GATE_VDEC1(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "vdec_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	GATE_VDEC1(CLK_VDEC_IMGRZ_CKEN, "vdec_imgrz_cken", "vdec_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static int clk_mt2712_vdec_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 			clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	if (r != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 			__func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static const struct of_device_id of_match_clk_mt2712_vdec[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	{ .compatible = "mediatek,mt2712-vdecsys", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static struct platform_driver clk_mt2712_vdec_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	.probe = clk_mt2712_vdec_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 		.name = "clk-mt2712-vdec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 		.of_match_table = of_match_clk_mt2712_vdec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) builtin_platform_driver(clk_mt2712_vdec_drv);