^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2017 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Weiyi Lu <weiyi.lu@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <dt-bindings/clock/mt2712-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static const struct mtk_gate_regs bdp_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) .set_ofs = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) .clr_ofs = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) .sta_ofs = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define GATE_BDP(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .regs = &bdp_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .ops = &mtk_clk_gate_ops_no_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static const struct mtk_gate bdp_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) GATE_BDP(CLK_BDP_BRIDGE_B, "bdp_bridge_b", "mm_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) GATE_BDP(CLK_BDP_BRIDGE_DRAM, "bdp_bridge_d", "mm_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) GATE_BDP(CLK_BDP_LARB_DRAM, "bdp_larb_d", "mm_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_PXL, "bdp_vdi_pxl", "tvd_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_DRAM, "bdp_vdi_d", "mm_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_B, "bdp_vdi_b", "mm_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) GATE_BDP(CLK_BDP_MT_B, "bdp_fmt_b", "mm_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) GATE_BDP(CLK_BDP_DISPFMT_27M, "bdp_27m", "di_sel", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) GATE_BDP(CLK_BDP_DISPFMT_27M_VDOUT, "bdp_27m_vdout", "di_sel", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) GATE_BDP(CLK_BDP_DISPFMT_27_74_74, "bdp_27_74_74", "di_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) GATE_BDP(CLK_BDP_DISPFMT_2FS, "bdp_2fs", "di_sel", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) GATE_BDP(CLK_BDP_DISPFMT_2FS_2FS74_148, "bdp_2fs74_148", "di_sel", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) GATE_BDP(CLK_BDP_DISPFMT_B, "bdp_b", "mm_sel", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) GATE_BDP(CLK_BDP_VDO_DRAM, "bdp_vdo_d", "mm_sel", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) GATE_BDP(CLK_BDP_VDO_2FS, "bdp_vdo_2fs", "di_sel", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) GATE_BDP(CLK_BDP_VDO_B, "bdp_vdo_b", "mm_sel", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) GATE_BDP(CLK_BDP_WR_CHANNEL_DI_PXL, "bdp_di_pxl", "di_sel", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) GATE_BDP(CLK_BDP_WR_CHANNEL_DI_DRAM, "bdp_di_d", "mm_sel", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) GATE_BDP(CLK_BDP_WR_CHANNEL_DI_B, "bdp_di_b", "mm_sel", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) GATE_BDP(CLK_BDP_NR_AGENT, "bdp_nr_agent", "nr_sel", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) GATE_BDP(CLK_BDP_NR_DRAM, "bdp_nr_d", "mm_sel", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) GATE_BDP(CLK_BDP_NR_B, "bdp_nr_b", "mm_sel", 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) GATE_BDP(CLK_BDP_BRIDGE_RT_B, "bdp_bridge_rt_b", "mm_sel", 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) GATE_BDP(CLK_BDP_BRIDGE_RT_DRAM, "bdp_bridge_rt_d", "mm_sel", 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) GATE_BDP(CLK_BDP_LARB_RT_DRAM, "bdp_larb_rt_d", "mm_sel", 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) GATE_BDP(CLK_BDP_TVD_TDC, "bdp_tvd_tdc", "mm_sel", 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) GATE_BDP(CLK_BDP_TVD_54, "bdp_tvd_clk_54", "tvd_sel", 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) GATE_BDP(CLK_BDP_TVD_CBUS, "bdp_tvd_cbus", "mm_sel", 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int clk_mt2712_bdp_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) clk_data = mtk_alloc_clk_data(CLK_BDP_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (r != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) pr_err("%s(): could not register clock provider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const struct of_device_id of_match_clk_mt2712_bdp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { .compatible = "mediatek,mt2712-bdpsys", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static struct platform_driver clk_mt2712_bdp_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .probe = clk_mt2712_bdp_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .name = "clk-mt2712-bdp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .of_match_table = of_match_clk_mt2712_bdp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) builtin_platform_driver(clk_mt2712_bdp_drv);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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