^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Shunli Wang <shunli.wang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <dt-bindings/clock/mt2701-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static const struct mtk_gate_regs disp0_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) .set_ofs = 0x0104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) .clr_ofs = 0x0108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) .sta_ofs = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static const struct mtk_gate_regs disp1_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .set_ofs = 0x0114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .clr_ofs = 0x0118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .sta_ofs = 0x0110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GATE_DISP0(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .regs = &disp0_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GATE_DISP1(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .regs = &disp1_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .ops = &mtk_clk_gate_ops_setclr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static const struct mtk_gate mm_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) GATE_DISP0(CLK_MM_SMI_COMMON, "mm_smi_comm", "mm_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) GATE_DISP0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) GATE_DISP0(CLK_MM_CMDQ, "mm_cmdq", "mm_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) GATE_DISP0(CLK_MM_MUTEX, "mm_mutex", "mm_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) GATE_DISP0(CLK_MM_DISP_COLOR, "mm_disp_color", "mm_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) GATE_DISP0(CLK_MM_DISP_BLS, "mm_disp_bls", "mm_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) GATE_DISP0(CLK_MM_DISP_WDMA, "mm_disp_wdma", "mm_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) GATE_DISP0(CLK_MM_DISP_RDMA, "mm_disp_rdma", "mm_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) GATE_DISP0(CLK_MM_DISP_OVL, "mm_disp_ovl", "mm_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) GATE_DISP0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) GATE_DISP0(CLK_MM_MDP_WROT, "mm_mdp_wrot", "mm_sel", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) GATE_DISP0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) GATE_DISP0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) GATE_DISP0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) GATE_DISP0(CLK_MM_MDP_RDMA, "mm_mdp_rdma", "mm_sel", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) GATE_DISP0(CLK_MM_MDP_BLS_26M, "mm_mdp_bls_26m", "pwm_sel", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) GATE_DISP0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) GATE_DISP0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) GATE_DISP0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "rtc_sel", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) GATE_DISP0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) GATE_DISP0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) GATE_DISP1(CLK_MM_DSI_ENGINE, "mm_dsi_eng", "mm_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) GATE_DISP1(CLK_MM_DSI_DIG, "mm_dsi_dig", "dsi0_lntc_dsi", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) GATE_DISP1(CLK_MM_DPI_DIGL, "mm_dpi_digl", "dpi0_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) GATE_DISP1(CLK_MM_DPI_ENGINE, "mm_dpi_eng", "mm_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) GATE_DISP1(CLK_MM_DPI1_DIGL, "mm_dpi1_digl", "dpi1_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) GATE_DISP1(CLK_MM_DPI1_ENGINE, "mm_dpi1_eng", "mm_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) GATE_DISP1(CLK_MM_TVE_OUTPUT, "mm_tve_output", "tve_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) GATE_DISP1(CLK_MM_TVE_INPUT, "mm_tve_input", "dpi0_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) GATE_DISP1(CLK_MM_HDMI_PIXEL, "mm_hdmi_pixel", "dpi1_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) GATE_DISP1(CLK_MM_HDMI_PLL, "mm_hdmi_pll", "hdmi_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) GATE_DISP1(CLK_MM_HDMI_AUDIO, "mm_hdmi_audio", "apll_sel", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) GATE_DISP1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll_sel", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) GATE_DISP1(CLK_MM_TVE_FMM, "mm_tve_fmm", "mm_sel", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static int clk_mt2701_mm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct device_node *node = dev->parent->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) clk_data = mtk_alloc_clk_data(CLK_MM_NR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) "could not register clock provider: %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) pdev->name, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static struct platform_driver clk_mt2701_mm_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .probe = clk_mt2701_mm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .name = "clk-mt2701-mm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) builtin_platform_driver(clk_mt2701_mm_drv);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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