Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Author: Sean Wang <sean.wang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/clock/mt2701-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define GATE_G3D(_id, _name, _parent, _shift) {	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		.id = _id,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		.name = _name,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		.parent_name = _parent,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		.regs = &g3d_cg_regs,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		.shift = _shift,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		.ops = &mtk_clk_gate_ops_setclr,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static const struct mtk_gate_regs g3d_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	.sta_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	.set_ofs = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	.clr_ofs = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const struct mtk_gate g3d_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 			       clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 			"could not register clock provider: %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 			pdev->name, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	mtk_register_reset_controller(node, 1, 0xc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static const struct of_device_id of_match_clk_mt2701_g3d[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		.compatible = "mediatek,mt2701-g3dsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		.data = clk_mt2701_g3dsys_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		/* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int clk_mt2701_g3d_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	int (*clk_init)(struct platform_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	clk_init = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	if (!clk_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	r = clk_init(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 		dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 			"could not register clock provider: %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 			pdev->name, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 	return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static struct platform_driver clk_mt2701_g3d_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 	.probe = clk_mt2701_g3d_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 		.name = "clk-mt2701-g3d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 		.of_match_table = of_match_clk_mt2701_g3d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) builtin_platform_driver(clk_mt2701_g3d_drv);