Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2014 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Author: Shunli Wang <shunli.wang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <dt-bindings/clock/mt2701-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static const struct mtk_gate_regs eth_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	.sta_ofs = 0x0030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define GATE_ETH(_id, _name, _parent, _shift) {		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		.id = _id,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		.name = _name,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		.parent_name = _parent,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		.regs = &eth_cg_regs,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		.shift = _shift,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static const struct mtk_gate eth_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	GATE_ETH(CLK_ETHSYS_GP1, "gp1_clk", "ethpll_500m_ck", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	GATE_ETH(CLK_ETHSYS_PCM, "pcm_clk", "ethif_sel", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	GATE_ETH(CLK_ETHSYS_GDMA, "gdma_clk", "ethif_sel", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	GATE_ETH(CLK_ETHSYS_I2S, "i2s_clk", "ethif_sel", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static const struct of_device_id of_match_clk_mt2701_eth[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	{ .compatible = "mediatek,mt2701-ethsys", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static int clk_mt2701_eth_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 						clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 			"could not register clock provider: %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 			pdev->name, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	mtk_register_reset_controller(node, 1, 0x34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static struct platform_driver clk_mt2701_eth_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	.probe = clk_mt2701_eth_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 		.name = "clk-mt2701-eth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 		.of_match_table = of_match_clk_mt2701_eth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) builtin_platform_driver(clk_mt2701_eth_drv);