^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Shunli Wang <shunli.wang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <dt-bindings/clock/mt2701-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static const struct mtk_gate_regs bdp0_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) .set_ofs = 0x0104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) .clr_ofs = 0x0108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) .sta_ofs = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static const struct mtk_gate_regs bdp1_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .set_ofs = 0x0114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .clr_ofs = 0x0118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .sta_ofs = 0x0110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GATE_BDP0(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .regs = &bdp0_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .ops = &mtk_clk_gate_ops_setclr_inv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GATE_BDP1(_id, _name, _parent, _shift) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .parent_name = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .regs = &bdp1_cg_regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .ops = &mtk_clk_gate_ops_setclr_inv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static const struct mtk_gate bdp_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) GATE_BDP0(CLK_BDP_BRG_BA, "brg_baclk", "mm_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) GATE_BDP0(CLK_BDP_BRG_DRAM, "brg_dram", "mm_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) GATE_BDP0(CLK_BDP_LARB_DRAM, "larb_dram", "mm_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) GATE_BDP0(CLK_BDP_WR_VDI_PXL, "wr_vdi_pxl", "hdmi_0_deep340m", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) GATE_BDP0(CLK_BDP_WR_VDI_DRAM, "wr_vdi_dram", "mm_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) GATE_BDP0(CLK_BDP_WR_B, "wr_bclk", "mm_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) GATE_BDP0(CLK_BDP_DGI_IN, "dgi_in", "dpi1_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) GATE_BDP0(CLK_BDP_DGI_OUT, "dgi_out", "dpi1_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) GATE_BDP0(CLK_BDP_FMT_MAST_27, "fmt_mast_27", "dpi1_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) GATE_BDP0(CLK_BDP_FMT_B, "fmt_bclk", "mm_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) GATE_BDP0(CLK_BDP_OSD_B, "osd_bclk", "mm_sel", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) GATE_BDP0(CLK_BDP_OSD_DRAM, "osd_dram", "mm_sel", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) GATE_BDP0(CLK_BDP_OSD_AGENT, "osd_agent", "osd_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) GATE_BDP0(CLK_BDP_OSD_PXL, "osd_pxl", "dpi1_sel", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) GATE_BDP0(CLK_BDP_RLE_B, "rle_bclk", "mm_sel", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) GATE_BDP0(CLK_BDP_RLE_AGENT, "rle_agent", "mm_sel", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) GATE_BDP0(CLK_BDP_RLE_DRAM, "rle_dram", "mm_sel", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) GATE_BDP0(CLK_BDP_F27M, "f27m", "di_sel", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) GATE_BDP0(CLK_BDP_F27M_VDOUT, "f27m_vdout", "di_sel", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) GATE_BDP0(CLK_BDP_F27_74_74, "f27_74_74", "di_sel", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) GATE_BDP0(CLK_BDP_F2FS, "f2fs", "di_sel", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) GATE_BDP0(CLK_BDP_F2FS74_148, "f2fs74_148", "di_sel", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) GATE_BDP0(CLK_BDP_FB, "fbclk", "mm_sel", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) GATE_BDP0(CLK_BDP_VDO_DRAM, "vdo_dram", "mm_sel", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) GATE_BDP0(CLK_BDP_VDO_2FS, "vdo_2fs", "di_sel", 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) GATE_BDP0(CLK_BDP_VDO_B, "vdo_bclk", "mm_sel", 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) GATE_BDP0(CLK_BDP_WR_DI_PXL, "wr_di_pxl", "di_sel", 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) GATE_BDP0(CLK_BDP_WR_DI_DRAM, "wr_di_dram", "mm_sel", 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) GATE_BDP0(CLK_BDP_WR_DI_B, "wr_di_bclk", "mm_sel", 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) GATE_BDP0(CLK_BDP_NR_PXL, "nr_pxl", "nr_sel", 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) GATE_BDP0(CLK_BDP_NR_DRAM, "nr_dram", "mm_sel", 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) GATE_BDP0(CLK_BDP_NR_B, "nr_bclk", "mm_sel", 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) GATE_BDP1(CLK_BDP_RX_F, "rx_fclk", "hadds2_fbclk", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) GATE_BDP1(CLK_BDP_RX_X, "rx_xclk", "clk26m", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) GATE_BDP1(CLK_BDP_RXPDT, "rxpdtclk", "hdmi_0_pix340m", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) GATE_BDP1(CLK_BDP_RX_CSCL_N, "rx_cscl_n", "clk26m", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) GATE_BDP1(CLK_BDP_RX_CSCL, "rx_cscl", "clk26m", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) GATE_BDP1(CLK_BDP_RX_DDCSCL_N, "rx_ddcscl_n", "hdmi_scl_rx", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) GATE_BDP1(CLK_BDP_RX_DDCSCL, "rx_ddcscl", "hdmi_scl_rx", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) GATE_BDP1(CLK_BDP_RX_VCO, "rx_vcoclk", "hadds2pll_294m", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) GATE_BDP1(CLK_BDP_RX_DP, "rx_dpclk", "hdmi_0_pll340m", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) GATE_BDP1(CLK_BDP_RX_P, "rx_pclk", "hdmi_0_pll340m", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) GATE_BDP1(CLK_BDP_RX_M, "rx_mclk", "hadds2pll_294m", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) GATE_BDP1(CLK_BDP_RX_PLL, "rx_pllclk", "hdmi_0_pix340m", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) GATE_BDP1(CLK_BDP_BRG_RT_B, "brg_rt_bclk", "mm_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) GATE_BDP1(CLK_BDP_BRG_RT_DRAM, "brg_rt_dram", "mm_sel", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) GATE_BDP1(CLK_BDP_LARBRT_DRAM, "larbrt_dram", "mm_sel", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) GATE_BDP1(CLK_BDP_TMDS_SYN, "tmds_syn", "hdmi_0_pll340m", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) GATE_BDP1(CLK_BDP_HDMI_MON, "hdmi_mon", "hdmi_0_pll340m", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const struct of_device_id of_match_clk_mt2701_bdp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { .compatible = "mediatek,mt2701-bdpsys", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int clk_mt2701_bdp_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) clk_data = mtk_alloc_clk_data(CLK_BDP_NR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) "could not register clock provider: %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) pdev->name, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static struct platform_driver clk_mt2701_bdp_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .probe = clk_mt2701_bdp_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .name = "clk-mt2701-bdp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .of_match_table = of_match_clk_mt2701_bdp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) builtin_platform_driver(clk_mt2701_bdp_drv);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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