Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Ryder Lee <ryder.lee@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <dt-bindings/clock/mt2701-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define GATE_AUDIO0(_id, _name, _parent, _shift) {	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 		.id = _id,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 		.name = _name,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 		.parent_name = _parent,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 		.regs = &audio0_cg_regs,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 		.shift = _shift,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 		.ops = &mtk_clk_gate_ops_no_setclr,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define GATE_AUDIO1(_id, _name, _parent, _shift) {	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		.id = _id,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 		.name = _name,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		.parent_name = _parent,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		.regs = &audio1_cg_regs,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		.shift = _shift,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		.ops = &mtk_clk_gate_ops_no_setclr,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define GATE_AUDIO2(_id, _name, _parent, _shift) {	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		.id = _id,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		.name = _name,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		.parent_name = _parent,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		.regs = &audio2_cg_regs,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		.shift = _shift,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		.ops = &mtk_clk_gate_ops_no_setclr,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define GATE_AUDIO3(_id, _name, _parent, _shift) {	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		.id = _id,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		.name = _name,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		.parent_name = _parent,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		.regs = &audio3_cg_regs,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		.shift = _shift,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		.ops = &mtk_clk_gate_ops_no_setclr,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static const struct mtk_gate_regs audio0_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	.set_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	.clr_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	.sta_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static const struct mtk_gate_regs audio1_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.set_ofs = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	.clr_ofs = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	.sta_ofs = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static const struct mtk_gate_regs audio2_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	.set_ofs = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	.clr_ofs = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	.sta_ofs = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static const struct mtk_gate_regs audio3_cg_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	.set_ofs = 0x634,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	.clr_ofs = 0x634,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	.sta_ofs = 0x634,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static const struct mtk_gate audio_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	/* AUDIO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	GATE_AUDIO0(CLK_AUD_SPDF, "audio_spdf", "audpll_sel", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	GATE_AUDIO0(CLK_AUD_SPDF2, "audio_spdf2", "audpll_sel", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	GATE_AUDIO0(CLK_AUD_APLL, "audio_apll", "audpll_sel", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	/* AUDIO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	GATE_AUDIO1(CLK_AUD_I2SIN1, "audio_i2sin1", "aud_mux1_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	GATE_AUDIO1(CLK_AUD_I2SIN2, "audio_i2sin2", "aud_mux1_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	GATE_AUDIO1(CLK_AUD_I2SIN3, "audio_i2sin3", "aud_mux1_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	GATE_AUDIO1(CLK_AUD_I2SIN4, "audio_i2sin4", "aud_mux1_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	GATE_AUDIO1(CLK_AUD_I2SIN5, "audio_i2sin5", "aud_mux1_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	GATE_AUDIO1(CLK_AUD_I2SIN6, "audio_i2sin6", "aud_mux1_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	GATE_AUDIO1(CLK_AUD_I2SO1, "audio_i2so1", "aud_mux1_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	GATE_AUDIO1(CLK_AUD_I2SO2, "audio_i2so2", "aud_mux1_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	GATE_AUDIO1(CLK_AUD_I2SO3, "audio_i2so3", "aud_mux1_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	GATE_AUDIO1(CLK_AUD_I2SO4, "audio_i2so4", "aud_mux1_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	GATE_AUDIO1(CLK_AUD_I2SO5, "audio_i2so5", "aud_mux1_sel", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	GATE_AUDIO1(CLK_AUD_I2SO6, "audio_i2so6", "aud_mux1_sel", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	GATE_AUDIO1(CLK_AUD_ASRCI1, "audio_asrci1", "asm_h_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	GATE_AUDIO1(CLK_AUD_ASRCI2, "audio_asrci2", "asm_h_sel", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	GATE_AUDIO1(CLK_AUD_ASRCO1, "audio_asrco1", "asm_h_sel", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	GATE_AUDIO1(CLK_AUD_ASRCO2, "audio_asrco2", "asm_h_sel", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	GATE_AUDIO1(CLK_AUD_INTDIR, "audio_intdir", "intdir_sel", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	GATE_AUDIO1(CLK_AUD_A1SYS, "audio_a1sys", "aud_mux1_sel", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	GATE_AUDIO1(CLK_AUD_A2SYS, "audio_a2sys", "aud_mux2_sel", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	GATE_AUDIO1(CLK_AUD_AFE_CONN, "audio_afe_conn", "aud_mux1_sel", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	GATE_AUDIO1(CLK_AUD_AFE_MRGIF, "audio_afe_mrgif", "aud_mux1_sel", 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	/* AUDIO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	GATE_AUDIO2(CLK_AUD_MMIF_UL1, "audio_ul1", "aud_mux1_sel", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	GATE_AUDIO2(CLK_AUD_MMIF_UL2, "audio_ul2", "aud_mux1_sel", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	GATE_AUDIO2(CLK_AUD_MMIF_UL3, "audio_ul3", "aud_mux1_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	GATE_AUDIO2(CLK_AUD_MMIF_UL4, "audio_ul4", "aud_mux1_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	GATE_AUDIO2(CLK_AUD_MMIF_UL5, "audio_ul5", "aud_mux1_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	GATE_AUDIO2(CLK_AUD_MMIF_UL6, "audio_ul6", "aud_mux1_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	GATE_AUDIO2(CLK_AUD_MMIF_DL1, "audio_dl1", "aud_mux1_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	GATE_AUDIO2(CLK_AUD_MMIF_DL2, "audio_dl2", "aud_mux1_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	GATE_AUDIO2(CLK_AUD_MMIF_DL3, "audio_dl3", "aud_mux1_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	GATE_AUDIO2(CLK_AUD_MMIF_DL4, "audio_dl4", "aud_mux1_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	GATE_AUDIO2(CLK_AUD_MMIF_DL5, "audio_dl5", "aud_mux1_sel", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	GATE_AUDIO2(CLK_AUD_MMIF_DL6, "audio_dl6", "aud_mux1_sel", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	GATE_AUDIO2(CLK_AUD_MMIF_DLMCH, "audio_dlmch", "aud_mux1_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	GATE_AUDIO2(CLK_AUD_MMIF_ARB1, "audio_arb1", "aud_mux1_sel", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	GATE_AUDIO2(CLK_AUD_MMIF_AWB1, "audio_awb", "aud_mux1_sel", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	GATE_AUDIO2(CLK_AUD_MMIF_AWB2, "audio_awb2", "aud_mux1_sel", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	GATE_AUDIO2(CLK_AUD_MMIF_DAI, "audio_dai", "aud_mux1_sel", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	/* AUDIO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	GATE_AUDIO3(CLK_AUD_ASRCI3, "audio_asrci3", "asm_h_sel", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	GATE_AUDIO3(CLK_AUD_ASRCI4, "audio_asrci4", "asm_h_sel", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	GATE_AUDIO3(CLK_AUD_ASRCI5, "audio_asrci5", "asm_h_sel", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	GATE_AUDIO3(CLK_AUD_ASRCI6, "audio_asrci6", "asm_h_sel", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	GATE_AUDIO3(CLK_AUD_ASRCO3, "audio_asrco3", "asm_h_sel", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	GATE_AUDIO3(CLK_AUD_ASRCO4, "audio_asrco4", "asm_h_sel", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	GATE_AUDIO3(CLK_AUD_ASRCO5, "audio_asrco5", "asm_h_sel", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	GATE_AUDIO3(CLK_AUD_ASRCO6, "audio_asrco6", "asm_h_sel", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	GATE_AUDIO3(CLK_AUD_MEM_ASRC1, "audio_mem_asrc1", "asm_h_sel", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	GATE_AUDIO3(CLK_AUD_MEM_ASRC2, "audio_mem_asrc2", "asm_h_sel", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	GATE_AUDIO3(CLK_AUD_MEM_ASRC3, "audio_mem_asrc3", "asm_h_sel", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	GATE_AUDIO3(CLK_AUD_MEM_ASRC4, "audio_mem_asrc4", "asm_h_sel", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	GATE_AUDIO3(CLK_AUD_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static const struct of_device_id of_match_clk_mt2701_aud[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	{ .compatible = "mediatek,mt2701-audsys", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int clk_mt2701_aud_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	clk_data = mtk_alloc_clk_data(CLK_AUD_NR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			       clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			"could not register clock provider: %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			pdev->name, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		goto err_clk_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	r = devm_of_platform_populate(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		goto err_plat_populate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) err_plat_populate:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	of_clk_del_provider(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) err_clk_provider:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static struct platform_driver clk_mt2701_aud_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	.probe = clk_mt2701_aud_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		.name = "clk-mt2701-aud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		.of_match_table = of_match_clk_mt2701_aud,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) builtin_platform_driver(clk_mt2701_aud_drv);