^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: James Liao <jamesjj.liao@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk-gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static int mtk_cg_bit_is_cleared(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) regmap_read(cg->regmap, cg->sta_ofs, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) val &= BIT(cg->bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) return val == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static int mtk_cg_bit_is_set(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) regmap_read(cg->regmap, cg->sta_ofs, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) val &= BIT(cg->bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return val != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static void mtk_cg_set_bit(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static void mtk_cg_clr_bit(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 cgbit = BIT(cg->bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) regmap_update_bits(cg->regmap, cg->sta_ofs, cgbit, cgbit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 cgbit = BIT(cg->bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) regmap_update_bits(cg->regmap, cg->sta_ofs, cgbit, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int mtk_cg_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) mtk_cg_clr_bit(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static void mtk_cg_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) mtk_cg_set_bit(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int mtk_cg_enable_inv(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) mtk_cg_set_bit(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static void mtk_cg_disable_inv(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) mtk_cg_clr_bit(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int mtk_cg_enable_no_setclr(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) mtk_cg_clr_bit_no_setclr(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void mtk_cg_disable_no_setclr(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) mtk_cg_set_bit_no_setclr(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int mtk_cg_enable_inv_no_setclr(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mtk_cg_set_bit_no_setclr(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void mtk_cg_disable_inv_no_setclr(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) mtk_cg_clr_bit_no_setclr(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) const struct clk_ops mtk_clk_gate_ops_setclr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .is_enabled = mtk_cg_bit_is_cleared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .enable = mtk_cg_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .disable = mtk_cg_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .is_enabled = mtk_cg_bit_is_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .enable = mtk_cg_enable_inv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .disable = mtk_cg_disable_inv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) const struct clk_ops mtk_clk_gate_ops_no_setclr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .is_enabled = mtk_cg_bit_is_cleared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .enable = mtk_cg_enable_no_setclr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .disable = mtk_cg_disable_no_setclr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) const struct clk_ops mtk_clk_gate_ops_no_setclr_inv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .is_enabled = mtk_cg_bit_is_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .enable = mtk_cg_enable_inv_no_setclr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .disable = mtk_cg_disable_inv_no_setclr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct clk *mtk_clk_register_gate(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int set_ofs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int clr_ofs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int sta_ofs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u8 bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) const struct clk_ops *ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct mtk_clk_gate *cg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct clk_init_data init = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) cg = kzalloc(sizeof(*cg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (!cg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) init.flags = flags | CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) init.parent_names = parent_name ? &parent_name : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) init.num_parents = parent_name ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) init.ops = ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) cg->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) cg->set_ofs = set_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) cg->clr_ofs = clr_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) cg->sta_ofs = sta_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) cg->bit = bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) cg->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) clk = clk_register(dev, &cg->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) kfree(cg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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