Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2015 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Author: James Liao <jamesjj.liao@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "clk-mtk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define REF2USB_TX_EN		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define REF2USB_TX_LPF_EN	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define REF2USB_TX_OUT_EN	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define REF2USB_EN_MASK		(REF2USB_TX_EN | REF2USB_TX_LPF_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 				 REF2USB_TX_OUT_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct mtk_ref2usb_tx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	struct clk_hw	hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	void __iomem	*base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static inline struct mtk_ref2usb_tx *to_mtk_ref2usb_tx(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	return container_of(hw, struct mtk_ref2usb_tx, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static int mtk_ref2usb_tx_is_prepared(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	struct mtk_ref2usb_tx *tx = to_mtk_ref2usb_tx(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	return (readl(tx->base_addr) & REF2USB_EN_MASK) == REF2USB_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int mtk_ref2usb_tx_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	struct mtk_ref2usb_tx *tx = to_mtk_ref2usb_tx(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	val = readl(tx->base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	val |= REF2USB_TX_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	writel(val, tx->base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	val |= REF2USB_TX_LPF_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	writel(val, tx->base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	val |= REF2USB_TX_OUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	writel(val, tx->base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static void mtk_ref2usb_tx_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	struct mtk_ref2usb_tx *tx = to_mtk_ref2usb_tx(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	val = readl(tx->base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	val &= ~REF2USB_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	writel(val, tx->base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static const struct clk_ops mtk_ref2usb_tx_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	.is_prepared	= mtk_ref2usb_tx_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	.prepare	= mtk_ref2usb_tx_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	.unprepare	= mtk_ref2usb_tx_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct clk * __init mtk_clk_register_ref2usb_tx(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 			const char *parent_name, void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	struct mtk_ref2usb_tx *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	struct clk_init_data init = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	tx = kzalloc(sizeof(*tx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	if (!tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 		return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 	tx->base_addr = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 	tx->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 	init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 	init.ops = &mtk_ref2usb_tx_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 	init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 	init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 	clk = clk_register(NULL, &tx->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 	if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 		pr_err("Failed to register clk %s: %ld\n", name, PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 		kfree(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) 	return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }