^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016 Yang Ling <gnaygnil@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <loongson1.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define OSC (24 * 1000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DIV_APB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static DEFINE_SPINLOCK(_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u32 pll, rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) pll = __raw_readl(LS1X_CLK_PLL_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) rate = ((pll >> 8) & 0xff) + ((pll >> 16) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) rate *= OSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) rate >>= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static const struct clk_ops ls1x_pll_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .recalc_rate = ls1x_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const struct clk_div_table ahb_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) [0] = { .val = 0, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) [1] = { .val = 1, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) [2] = { .val = 2, .div = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) [3] = { .val = 3, .div = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) [4] = { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) void __init ls1x_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) hw = clk_hw_register_fixed_rate(NULL, "osc_clk", NULL, 0, OSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) clk_hw_register_clkdev(hw, "osc_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* clock derived from 24 MHz OSC clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) hw = clk_hw_register_pll(NULL, "pll_clk", "osc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) &ls1x_pll_clk_ops, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) clk_hw_register_clkdev(hw, "pll_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) hw = clk_hw_register_divider(NULL, "cpu_clk_div", "pll_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) CLK_GET_RATE_NOCACHE, LS1X_CLK_PLL_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) DIV_CPU_SHIFT, DIV_CPU_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) CLK_DIVIDER_ONE_BASED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) CLK_DIVIDER_ROUND_CLOSEST, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) clk_hw_register_clkdev(hw, "cpu_clk_div", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) hw = clk_hw_register_fixed_factor(NULL, "cpu_clk", "cpu_clk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 0, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) clk_hw_register_clkdev(hw, "cpu_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) hw = clk_hw_register_divider(NULL, "dc_clk_div", "pll_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 0, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) clk_hw_register_clkdev(hw, "dc_clk_div", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) hw = clk_hw_register_fixed_factor(NULL, "dc_clk", "dc_clk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 0, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) clk_hw_register_clkdev(hw, "dc_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) hw = clk_hw_register_divider_table(NULL, "ahb_clk_div", "cpu_clk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 0, LS1X_CLK_PLL_FREQ, DIV_DDR_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) DIV_DDR_WIDTH, CLK_DIVIDER_ALLOW_ZERO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ahb_div_table, &_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) clk_hw_register_clkdev(hw, "ahb_clk_div", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) hw = clk_hw_register_fixed_factor(NULL, "ahb_clk", "ahb_clk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 0, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) clk_hw_register_clkdev(hw, "ahb_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) clk_hw_register_clkdev(hw, "ls1x-dma", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) clk_hw_register_clkdev(hw, "stmmaceth", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* clock derived from AHB clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) hw = clk_hw_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) DIV_APB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) clk_hw_register_clkdev(hw, "apb_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) clk_hw_register_clkdev(hw, "ls1x-ac97", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) clk_hw_register_clkdev(hw, "ls1x-i2c", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) clk_hw_register_clkdev(hw, "ls1x-nand", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) clk_hw_register_clkdev(hw, "ls1x-pwmtimer", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) clk_hw_register_clkdev(hw, "ls1x-spi", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) clk_hw_register_clkdev(hw, "ls1x-wdt", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) clk_hw_register_clkdev(hw, "serial8250", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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