^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct ti_syscon_gate_clk_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) u32 idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct ti_syscon_gate_clk_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u32 bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ti_syscon_gate_clk_priv *to_ti_syscon_gate_clk_priv(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) return container_of(hw, struct ti_syscon_gate_clk_priv, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static int ti_syscon_gate_clk_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct ti_syscon_gate_clk_priv *priv = to_ti_syscon_gate_clk_priv(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) return regmap_write_bits(priv->regmap, priv->reg, priv->idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) priv->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static void ti_syscon_gate_clk_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct ti_syscon_gate_clk_priv *priv = to_ti_syscon_gate_clk_priv(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) regmap_write_bits(priv->regmap, priv->reg, priv->idx, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int ti_syscon_gate_clk_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct ti_syscon_gate_clk_priv *priv = to_ti_syscon_gate_clk_priv(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) regmap_read(priv->regmap, priv->reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return !!(val & priv->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static const struct clk_ops ti_syscon_gate_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .enable = ti_syscon_gate_clk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .disable = ti_syscon_gate_clk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .is_enabled = ti_syscon_gate_clk_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static struct clk_hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *ti_syscon_gate_clk_register(struct device *dev, struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) const struct ti_syscon_gate_clk_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct ti_syscon_gate_clk_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) init.name = data->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) init.ops = &ti_syscon_gate_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) init.parent_names = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) init.num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) priv->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) priv->reg = data->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) priv->idx = BIT(data->bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) priv->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ret = devm_clk_hw_register(dev, &priv->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return &priv->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int ti_syscon_gate_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) const struct ti_syscon_gate_clk_data *data, *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct clk_hw_onecell_data *hw_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int num_clks, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) data = device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) regmap = syscon_node_to_regmap(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (PTR_ERR(regmap) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) dev_err(dev, "failed to find parent regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) num_clks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) for (p = data; p->name; p++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) num_clks++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, num_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (!hw_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) hw_data->num = num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) for (i = 0; i < num_clks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) hw_data->hws[i] = ti_syscon_gate_clk_register(dev, regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) &data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (IS_ERR(hw_data->hws[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dev_warn(dev, "failed to register %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) data[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) hw_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TI_SYSCON_CLK_GATE(_name, _offset, _bit_idx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .offset = (_offset), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .bit_idx = (_bit_idx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const struct ti_syscon_gate_clk_data am654_clk_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) TI_SYSCON_CLK_GATE("ehrpwm_tbclk0", 0x0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) TI_SYSCON_CLK_GATE("ehrpwm_tbclk1", 0x4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) TI_SYSCON_CLK_GATE("ehrpwm_tbclk2", 0x8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) TI_SYSCON_CLK_GATE("ehrpwm_tbclk3", 0xc, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) TI_SYSCON_CLK_GATE("ehrpwm_tbclk4", 0x10, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) TI_SYSCON_CLK_GATE("ehrpwm_tbclk5", 0x14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { /* Sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const struct of_device_id ti_syscon_gate_clk_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .compatible = "ti,am654-ehrpwm-tbclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .data = &am654_clk_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MODULE_DEVICE_TABLE(of, ti_syscon_gate_clk_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static struct platform_driver ti_syscon_gate_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .probe = ti_syscon_gate_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .name = "ti-syscon-gate-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .of_match_table = ti_syscon_gate_clk_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) module_platform_driver(ti_syscon_gate_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) MODULE_DESCRIPTION("Syscon backed gate-clock driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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