Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * PLL clock driver for Keystone devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2013 Texas Instruments Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *	Murali Karicheri <m-karicheri2@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *	Santosh Shilimkar <santosh.shilimkar@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define PLLM_LOW_MASK		0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define PLLM_HIGH_MASK		0x7ffc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define MAIN_PLLM_HIGH_MASK	0x7f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define PLLM_HIGH_SHIFT		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define PLLD_MASK		0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CLKOD_MASK		0x780000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CLKOD_SHIFT		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * struct clk_pll_data - pll data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * @has_pllctrl: If set to non zero, lower 6 bits of multiplier is in pllm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *	register of pll controller, else it is in the pll_ctrl0((bit 11-6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * @phy_pllm: Physical address of PLLM in pll controller. Used when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *	has_pllctrl is non zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * @phy_pll_ctl0: Physical address of PLL ctrl0. This could be that of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  *	Main PLL or any other PLLs in the device such as ARM PLL, DDR PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  *	or PA PLL available on keystone2. These PLLs are controlled by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  *	this register. Main PLL is controlled by a PLL controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * @pllm: PLL register map address for multiplier bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * @pllod: PLL register map address for post divider bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * @pll_ctl0: PLL controller map address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * @pllm_lower_mask: multiplier lower mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * @pllm_upper_mask: multiplier upper mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * @pllm_upper_shift: multiplier upper shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * @plld_mask: divider mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * @clkod_mask: output divider mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * @clkod_shift: output divider shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * @plld_mask: divider mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * @postdiv: Fixed post divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) struct clk_pll_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	bool has_pllctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	u32 phy_pllm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	u32 phy_pll_ctl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	void __iomem *pllm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	void __iomem *pllod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	void __iomem *pll_ctl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	u32 pllm_lower_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	u32 pllm_upper_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	u32 pllm_upper_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u32 plld_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	u32 clkod_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	u32 clkod_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	u32 postdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  * struct clk_pll - Main pll clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * @hw: clk_hw for the pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  * @pll_data: PLL driver specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) struct clk_pll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct clk_pll_data *pll_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static unsigned long clk_pllclk_recalc(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 					unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	struct clk_pll_data *pll_data = pll->pll_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	unsigned long rate = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u32  mult = 0, prediv, postdiv, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	 * get bits 0-5 of multiplier from pllctrl PLLM register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	 * if has_pllctrl is non zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	if (pll_data->has_pllctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		val = readl(pll_data->pllm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		mult = (val & pll_data->pllm_lower_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	/* bit6-12 of PLLM is in Main PLL control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	val = readl(pll_data->pll_ctl0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	mult |= ((val & pll_data->pllm_upper_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			>> pll_data->pllm_upper_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	prediv = (val & pll_data->plld_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	if (!pll_data->has_pllctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		/* read post divider from od bits*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		postdiv = ((val & pll_data->clkod_mask) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 				 pll_data->clkod_shift) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	else if (pll_data->pllod) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		postdiv = readl(pll_data->pllod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		postdiv = ((postdiv & pll_data->clkod_mask) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 				pll_data->clkod_shift) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		postdiv = pll_data->postdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	rate /= (prediv + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	rate = (rate * (mult + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	rate /= postdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const struct clk_ops clk_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.recalc_rate = clk_pllclk_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static struct clk *clk_register_pll(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			struct clk_pll_data *pll_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	struct clk_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (!pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	init.ops = &clk_pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	init.parent_names = (parent_name ? &parent_name : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	init.num_parents = (parent_name ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	pll->pll_data	= pll_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	pll->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	clk = clk_register(NULL, &pll->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  * _of_pll_clk_init - PLL initialisation via DT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  * @node: device tree node for this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  * @pllctrl: If true, lower 6 bits of multiplier is in pllm register of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  *		pll controller, else it is in the control register0(bit 11-6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	struct clk_pll_data *pll_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	pll_data = kzalloc(sizeof(*pll_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	if (!pll_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		pr_err("%s: Out of memory\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	parent_name = of_clk_get_parent_name(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	if (of_property_read_u32(node, "fixed-postdiv",	&pll_data->postdiv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		/* assume the PLL has output divider register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		pll_data->clkod_mask = CLKOD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		pll_data->clkod_shift = CLKOD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		 * Check if there is an post-divider register. If not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		 * assume od bits are part of control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		i = of_property_match_string(node, "reg-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 					     "post-divider");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		pll_data->pllod = of_iomap(node, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	i = of_property_match_string(node, "reg-names", "control");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	pll_data->pll_ctl0 = of_iomap(node, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	if (!pll_data->pll_ctl0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		pr_err("%s: ioremap failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		iounmap(pll_data->pllod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	pll_data->pllm_lower_mask = PLLM_LOW_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	pll_data->pllm_upper_shift = PLLM_HIGH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	pll_data->plld_mask = PLLD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	pll_data->has_pllctrl = pllctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (!pll_data->has_pllctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		pll_data->pllm_upper_mask = PLLM_HIGH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		pll_data->pllm_upper_mask = MAIN_PLLM_HIGH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		i = of_property_match_string(node, "reg-names", "multiplier");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		pll_data->pllm = of_iomap(node, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		if (!pll_data->pllm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			iounmap(pll_data->pll_ctl0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			iounmap(pll_data->pllod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	clk = clk_register_pll(NULL, node->name, parent_name, pll_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		of_clk_add_provider(node, of_clk_src_simple_get, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	pr_err("%s: error initializing pll %pOFn\n", __func__, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	kfree(pll_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)  * of_keystone_pll_clk_init - PLL initialisation DT wrapper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)  * @node: device tree node for this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static void __init of_keystone_pll_clk_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	_of_pll_clk_init(node, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) CLK_OF_DECLARE(keystone_pll_clock, "ti,keystone,pll-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 					of_keystone_pll_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)  * of_keystone_main_pll_clk_init - Main PLL initialisation DT wrapper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)  * @node: device tree node for this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static void __init of_keystone_main_pll_clk_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	_of_pll_clk_init(node, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) CLK_OF_DECLARE(keystone_main_pll_clock, "ti,keystone,main-pll-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 						of_keystone_main_pll_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)  * of_pll_div_clk_init - PLL divider setup function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)  * @node: device tree node for this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static void __init of_pll_div_clk_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	u32 shift, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	const char *clk_name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	of_property_read_string(node, "clock-output-names", &clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	reg = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (!reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		pr_err("%s: ioremap failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	parent_name = of_clk_get_parent_name(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	if (!parent_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		pr_err("%s: missing parent clock\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		iounmap(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	if (of_property_read_u32(node, "bit-shift", &shift)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		pr_err("%s: missing 'shift' property\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		iounmap(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	if (of_property_read_u32(node, "bit-mask", &mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		pr_err("%s: missing 'bit-mask' property\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		iounmap(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	clk = clk_register_divider(NULL, clk_name, parent_name, 0, reg, shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 				 mask, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	if (clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		of_clk_add_provider(node, of_clk_src_simple_get, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		pr_err("%s: error registering divider %s\n", __func__, clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		iounmap(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) CLK_OF_DECLARE(pll_divider_clock, "ti,keystone,pll-divider-clock", of_pll_div_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)  * of_pll_mux_clk_init - PLL mux setup function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)  * @node: device tree node for this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static void __init of_pll_mux_clk_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	u32 shift, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	const char *parents[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	const char *clk_name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	of_property_read_string(node, "clock-output-names", &clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	reg = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	if (!reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		pr_err("%s: ioremap failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	of_clk_parent_fill(node, parents, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	if (!parents[0] || !parents[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		pr_err("%s: missing parent clocks\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	if (of_property_read_u32(node, "bit-shift", &shift)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		pr_err("%s: missing 'shift' property\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	if (of_property_read_u32(node, "bit-mask", &mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		pr_err("%s: missing 'bit-mask' property\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	clk = clk_register_mux(NULL, clk_name, (const char **)&parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 				ARRAY_SIZE(parents) , 0, reg, shift, mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 				0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	if (clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		of_clk_add_provider(node, of_clk_src_simple_get, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		pr_err("%s: error registering mux %s\n", __func__, clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) CLK_OF_DECLARE(pll_mux_clock, "ti,keystone,pll-mux-clock", of_pll_mux_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) MODULE_DESCRIPTION("PLL clock driver for Keystone devices");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) MODULE_AUTHOR("Murali Karicheri <m-karicheri2@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MODULE_AUTHOR("Santosh Shilimkar <santosh.shilimkar@ti.com>");