^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Clock driver for Keystone 2 based devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Texas Instruments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Murali Karicheri <m-karicheri2@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Santosh Shilimkar <santosh.shilimkar@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* PSC register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PTCMD 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PTSTAT 0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PDSTAT 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PDCTL 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MDSTAT 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MDCTL 0xa00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* PSC module states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PSC_STATE_SWRSTDISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PSC_STATE_SYNCRST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PSC_STATE_DISABLE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PSC_STATE_ENABLE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MDSTAT_STATE_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MDSTAT_MCKOUT BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PDSTAT_STATE_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MDCTL_FORCE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MDCTL_LRESET BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PDCTL_NEXT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Maximum timeout to bail out state transition for module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define STATE_TRANS_MAX_COUNT 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static void __iomem *domain_transition_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * struct clk_psc_data - PSC data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @control_base: Base address for a PSC control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * @domain_base: Base address for a PSC domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @domain_id: PSC domain id number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct clk_psc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) void __iomem *control_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) void __iomem *domain_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 domain_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * struct clk_psc - PSC clock structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @hw: clk_hw for the psc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @psc_data: PSC driver specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @lock: Spinlock used by the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct clk_psc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct clk_psc_data *psc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static DEFINE_SPINLOCK(psc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define to_clk_psc(_hw) container_of(_hw, struct clk_psc, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static void psc_config(void __iomem *control_base, void __iomem *domain_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 next_state, u32 domain_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 ptcmd, pdstat, pdctl, mdstat, mdctl, ptstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 count = STATE_TRANS_MAX_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) mdctl = readl(control_base + MDCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) mdctl &= ~MDSTAT_STATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) mdctl |= next_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* For disable, we always put the module in local reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (next_state == PSC_STATE_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) mdctl &= ~MDCTL_LRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) writel(mdctl, control_base + MDCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) pdstat = readl(domain_base + PDSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (!(pdstat & PDSTAT_STATE_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) pdctl = readl(domain_base + PDCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) pdctl |= PDCTL_NEXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) writel(pdctl, domain_base + PDCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ptcmd = 1 << domain_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) writel(ptcmd, domain_transition_base + PTCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ptstat = readl(domain_transition_base + PTSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) } while (((ptstat >> domain_id) & 1) && count--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) count = STATE_TRANS_MAX_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) mdstat = readl(control_base + MDSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) } while (!((mdstat & MDSTAT_STATE_MASK) == next_state) && count--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int keystone_clk_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct clk_psc *psc = to_clk_psc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct clk_psc_data *data = psc->psc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 mdstat = readl(data->control_base + MDSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return (mdstat & MDSTAT_MCKOUT) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int keystone_clk_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct clk_psc *psc = to_clk_psc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct clk_psc_data *data = psc->psc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (psc->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) spin_lock_irqsave(psc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) psc_config(data->control_base, data->domain_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PSC_STATE_ENABLE, data->domain_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (psc->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) spin_unlock_irqrestore(psc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void keystone_clk_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct clk_psc *psc = to_clk_psc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct clk_psc_data *data = psc->psc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (psc->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) spin_lock_irqsave(psc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) psc_config(data->control_base, data->domain_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PSC_STATE_DISABLE, data->domain_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (psc->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) spin_unlock_irqrestore(psc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const struct clk_ops clk_psc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .enable = keystone_clk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .disable = keystone_clk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .is_enabled = keystone_clk_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * clk_register_psc - register psc clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * @dev: device that is registering this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * @name: name of this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * @parent_name: name of clock's parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * @psc_data: platform data to configure this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * @lock: spinlock used by this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static struct clk *clk_register_psc(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct clk_psc_data *psc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct clk_psc *psc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) psc = kzalloc(sizeof(*psc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (!psc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) init.ops = &clk_psc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) init.parent_names = (parent_name ? &parent_name : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) init.num_parents = (parent_name ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) psc->psc_data = psc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) psc->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) psc->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) clk = clk_register(NULL, &psc->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) kfree(psc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * of_psc_clk_init - initialize psc clock through DT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * @node: device tree node for this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * @lock: spinlock used by this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static void __init of_psc_clk_init(struct device_node *node, spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) const char *clk_name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct clk_psc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) data = kzalloc(sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (!data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) pr_err("%s: Out of memory\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) i = of_property_match_string(node, "reg-names", "control");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) data->control_base = of_iomap(node, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (!data->control_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) pr_err("%s: control ioremap failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) i = of_property_match_string(node, "reg-names", "domain");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) data->domain_base = of_iomap(node, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (!data->domain_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) pr_err("%s: domain ioremap failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) goto unmap_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) of_property_read_u32(node, "domain-id", &data->domain_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Domain transition registers at fixed address space of domain_id 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (!domain_transition_base && !data->domain_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) domain_transition_base = data->domain_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) of_property_read_string(node, "clock-output-names", &clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) parent_name = of_clk_get_parent_name(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (!parent_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) pr_err("%s: Parent clock not found\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) goto unmap_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) clk = clk_register_psc(NULL, clk_name, parent_name, data, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (!IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) of_clk_add_provider(node, of_clk_src_simple_get, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) pr_err("%s: error registering clk %pOFn\n", __func__, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unmap_domain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) iounmap(data->domain_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unmap_ctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) iounmap(data->control_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * of_keystone_psc_clk_init - initialize psc clock through DT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * @node: device tree node for this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static void __init of_keystone_psc_clk_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) of_psc_clk_init(node, &psc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) CLK_OF_DECLARE(keystone_gate_clk, "ti,keystone,psc-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) of_keystone_psc_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MODULE_DESCRIPTION("Clock driver for Keystone 2 based devices");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MODULE_AUTHOR("Murali Karicheri <m-karicheri2@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MODULE_AUTHOR("Santosh Shilimkar <santosh.shilimkar@ti.com>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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