^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * X1830 SoC CGU driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/clock/x1830-cgu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "cgu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* CGU register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CGU_REG_CPCCR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CGU_REG_CPPCR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CGU_REG_APLL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CGU_REG_MPLL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CGU_REG_CLKGR0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CGU_REG_OPCR 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CGU_REG_CLKGR1 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CGU_REG_DDRCDR 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CGU_REG_USBPCR 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CGU_REG_USBRDT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CGU_REG_USBVBFIL 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CGU_REG_USBPCR1 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CGU_REG_MACCDR 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CGU_REG_EPLL 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CGU_REG_I2SCDR 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CGU_REG_LPCDR 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CGU_REG_MSC0CDR 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CGU_REG_I2SCDR1 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CGU_REG_SSICDR 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CGU_REG_CIMCDR 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CGU_REG_MSC1CDR 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CGU_REG_CMP_INTR 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CGU_REG_CMP_INTRE 0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CGU_REG_DRCG 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CGU_REG_CPCSR 0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CGU_REG_VPLL 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CGU_REG_MACPHYC 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* bits within the OPCR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OPCR_GATE_USBPHYCLK BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OPCR_SPENDN0 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OPCR_SPENDN1 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* bits within the USBPCR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define USBPCR_SIDDQ BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define USBPCR_OTG_DISABLE BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static struct ingenic_cgu *cgu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static int x1830_usb_phy_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) writel((readl(reg_opcr) | OPCR_SPENDN0) & ~OPCR_GATE_USBPHYCLK, reg_opcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) writel(readl(reg_usbpcr) & ~USBPCR_OTG_DISABLE & ~USBPCR_SIDDQ, reg_usbpcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static void x1830_usb_phy_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) writel((readl(reg_opcr) & ~OPCR_SPENDN0) | OPCR_GATE_USBPHYCLK, reg_opcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) writel(readl(reg_usbpcr) | USBPCR_OTG_DISABLE | USBPCR_SIDDQ, reg_usbpcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int x1830_usb_phy_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return (readl(reg_opcr) & OPCR_SPENDN0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) !(readl(reg_usbpcr) & USBPCR_SIDDQ) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) !(readl(reg_usbpcr) & USBPCR_OTG_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const struct clk_ops x1830_otg_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .enable = x1830_usb_phy_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .disable = x1830_usb_phy_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .is_enabled = x1830_usb_phy_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static const s8 pll_od_encoding[64] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) -1, -1, -1, -1, -1, -1, -1, 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) -1, -1, -1, -1, -1, -1, -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) -1, -1, -1, -1, -1, -1, -1, 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) -1, -1, -1, -1, -1, -1, -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) -1, -1, -1, -1, -1, -1, -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) -1, -1, -1, -1, -1, -1, -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) -1, -1, -1, -1, -1, -1, -1, 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* External clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [X1830_CLK_EXCLK] = { "ext", CGU_CLK_EXT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) [X1830_CLK_RTCLK] = { "rtc", CGU_CLK_EXT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* PLLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) [X1830_CLK_APLL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) "apll", CGU_CLK_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .reg = CGU_REG_APLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .rate_multiplier = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .m_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .m_bits = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .m_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .n_shift = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .n_bits = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .n_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .od_shift = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .od_bits = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .od_max = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .od_encoding = pll_od_encoding,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .bypass_reg = CGU_REG_CPPCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .bypass_bit = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .enable_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .stable_bit = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) [X1830_CLK_MPLL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "mpll", CGU_CLK_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .reg = CGU_REG_MPLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .rate_multiplier = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .m_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .m_bits = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .m_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .n_shift = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .n_bits = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .n_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .od_shift = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .od_bits = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .od_max = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .od_encoding = pll_od_encoding,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .bypass_reg = CGU_REG_CPPCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .bypass_bit = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .enable_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .stable_bit = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) [X1830_CLK_EPLL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "epll", CGU_CLK_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .reg = CGU_REG_EPLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .rate_multiplier = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .m_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .m_bits = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .m_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .n_shift = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .n_bits = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .n_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .od_shift = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .od_bits = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .od_max = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .od_encoding = pll_od_encoding,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .bypass_reg = CGU_REG_CPPCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .bypass_bit = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .enable_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .stable_bit = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) [X1830_CLK_VPLL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) "vpll", CGU_CLK_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .reg = CGU_REG_VPLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .rate_multiplier = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .m_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .m_bits = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .m_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .n_shift = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .n_bits = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .n_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .od_shift = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .od_bits = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .od_max = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .od_encoding = pll_od_encoding,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .bypass_reg = CGU_REG_CPPCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .bypass_bit = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .enable_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .stable_bit = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Custom (SoC-specific) OTG PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) [X1830_CLK_OTGPHY] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "otg_phy", CGU_CLK_CUSTOM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .custom = { &x1830_otg_phy_ops },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Muxes & dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) [X1830_CLK_SCLKA] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "sclk_a", CGU_CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .parents = { -1, X1830_CLK_EXCLK, X1830_CLK_APLL, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .mux = { CGU_REG_CPCCR, 30, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) [X1830_CLK_CPUMUX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "cpu_mux", CGU_CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .mux = { CGU_REG_CPCCR, 28, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) [X1830_CLK_CPU] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) "cpu", CGU_CLK_DIV | CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .parents = { X1830_CLK_CPUMUX, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .gate = { CGU_REG_CLKGR1, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) [X1830_CLK_L2CACHE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) "l2cache", CGU_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .parents = { X1830_CLK_CPUMUX, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) [X1830_CLK_AHB0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .mux = { CGU_REG_CPCCR, 26, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .div = { CGU_REG_CPCCR, 8, 1, 4, 21, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) [X1830_CLK_AHB2PMUX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) "ahb2_apb_mux", CGU_CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .mux = { CGU_REG_CPCCR, 24, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) [X1830_CLK_AHB2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) "ahb2", CGU_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .parents = { X1830_CLK_AHB2PMUX, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) [X1830_CLK_PCLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) "pclk", CGU_CLK_DIV | CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .parents = { X1830_CLK_AHB2PMUX, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .gate = { CGU_REG_CLKGR1, 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) [X1830_CLK_DDR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .mux = { CGU_REG_DDRCDR, 30, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .gate = { CGU_REG_CLKGR0, 31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) [X1830_CLK_MAC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) X1830_CLK_VPLL, X1830_CLK_EPLL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .mux = { CGU_REG_MACCDR, 30, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .div = { CGU_REG_MACCDR, 0, 1, 8, 29, 28, 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .gate = { CGU_REG_CLKGR1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) [X1830_CLK_LCD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) X1830_CLK_VPLL, X1830_CLK_EPLL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .mux = { CGU_REG_LPCDR, 30, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .div = { CGU_REG_LPCDR, 0, 1, 8, 28, 27, 26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .gate = { CGU_REG_CLKGR1, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) [X1830_CLK_MSCMUX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) "msc_mux", CGU_CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) X1830_CLK_VPLL, X1830_CLK_EPLL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .mux = { CGU_REG_MSC0CDR, 30, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) [X1830_CLK_MSC0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) "msc0", CGU_CLK_DIV | CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .parents = { X1830_CLK_MSCMUX, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .gate = { CGU_REG_CLKGR0, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) [X1830_CLK_MSC1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) "msc1", CGU_CLK_DIV | CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .parents = { X1830_CLK_MSCMUX, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .gate = { CGU_REG_CLKGR0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) [X1830_CLK_SSIPLL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) X1830_CLK_VPLL, X1830_CLK_EPLL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .mux = { CGU_REG_SSICDR, 30, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .div = { CGU_REG_SSICDR, 0, 1, 8, 28, 27, 26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) [X1830_CLK_SSIPLL_DIV2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) "ssi_pll_div2", CGU_CLK_FIXDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .parents = { X1830_CLK_SSIPLL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .fixdiv = { 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) [X1830_CLK_SSIMUX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) "ssi_mux", CGU_CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .parents = { X1830_CLK_EXCLK, X1830_CLK_SSIPLL_DIV2, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .mux = { CGU_REG_SSICDR, 29, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) [X1830_CLK_EXCLK_DIV512] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) "exclk_div512", CGU_CLK_FIXDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .parents = { X1830_CLK_EXCLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .fixdiv = { 512 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) [X1830_CLK_RTC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) "rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .parents = { X1830_CLK_EXCLK_DIV512, X1830_CLK_RTCLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .mux = { CGU_REG_OPCR, 2, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .gate = { CGU_REG_CLKGR0, 29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* Gate-only clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) [X1830_CLK_EMC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) "emc", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .parents = { X1830_CLK_AHB2, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .gate = { CGU_REG_CLKGR0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) [X1830_CLK_EFUSE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) "efuse", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .parents = { X1830_CLK_AHB2, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .gate = { CGU_REG_CLKGR0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) [X1830_CLK_OTG] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) "otg", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .gate = { CGU_REG_CLKGR0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) [X1830_CLK_SSI0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) "ssi0", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .parents = { X1830_CLK_SSIMUX, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .gate = { CGU_REG_CLKGR0, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) [X1830_CLK_SMB0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) "smb0", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .parents = { X1830_CLK_PCLK, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .gate = { CGU_REG_CLKGR0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) [X1830_CLK_SMB1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) "smb1", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .parents = { X1830_CLK_PCLK, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .gate = { CGU_REG_CLKGR0, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) [X1830_CLK_SMB2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) "smb2", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .parents = { X1830_CLK_PCLK, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .gate = { CGU_REG_CLKGR0, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) [X1830_CLK_UART0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) "uart0", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .gate = { CGU_REG_CLKGR0, 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) [X1830_CLK_UART1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) "uart1", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .gate = { CGU_REG_CLKGR0, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) [X1830_CLK_SSI1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) "ssi1", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .parents = { X1830_CLK_SSIMUX, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .gate = { CGU_REG_CLKGR0, 19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) [X1830_CLK_SFC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) "sfc", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .parents = { X1830_CLK_SSIPLL, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .gate = { CGU_REG_CLKGR0, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) [X1830_CLK_PDMA] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) "pdma", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .gate = { CGU_REG_CLKGR0, 21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) [X1830_CLK_TCU] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) "tcu", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .gate = { CGU_REG_CLKGR0, 30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) [X1830_CLK_DTRNG] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) "dtrng", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .parents = { X1830_CLK_PCLK, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .gate = { CGU_REG_CLKGR1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) [X1830_CLK_OST] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) "ost", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .gate = { CGU_REG_CLKGR1, 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static void __init x1830_cgu_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) cgu = ingenic_cgu_new(x1830_cgu_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ARRAY_SIZE(x1830_cgu_clocks), np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (!cgu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) pr_err("%s: failed to initialise CGU\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) retval = ingenic_cgu_register_clocks(cgu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) pr_err("%s: failed to register CGU Clocks\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ingenic_cgu_register_syscore_ops(cgu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * CGU has some children devices, this is useful for probing children devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * in the case where the device node is compatible with "simple-mfd".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) CLK_OF_DECLARE_DRIVER(x1830_cgu, "ingenic,x1830-cgu", x1830_cgu_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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