Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * X1000 SoC CGU driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <dt-bindings/clock/x1000-cgu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "cgu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /* CGU register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define CGU_REG_CPCCR		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define CGU_REG_APLL		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define CGU_REG_MPLL		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define CGU_REG_CLKGR		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CGU_REG_OPCR		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CGU_REG_DDRCDR		0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CGU_REG_USBPCR		0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CGU_REG_USBPCR1		0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CGU_REG_USBCDR		0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CGU_REG_MACCDR		0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CGU_REG_I2SCDR		0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CGU_REG_LPCDR		0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define CGU_REG_MSC0CDR		0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CGU_REG_I2SCDR1		0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CGU_REG_SSICDR		0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define CGU_REG_CIMCDR		0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define CGU_REG_PCMCDR		0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define CGU_REG_MSC1CDR		0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CGU_REG_CMP_INTR	0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CGU_REG_CMP_INTRE	0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CGU_REG_DRCG		0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CGU_REG_CPCSR		0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define CGU_REG_PCMCDR1		0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define CGU_REG_MACPHYC		0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /* bits within the OPCR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define OPCR_SPENDN0		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define OPCR_SPENDN1		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /* bits within the USBPCR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define USBPCR_SIDDQ		BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define USBPCR_OTG_DISABLE	BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) /* bits within the USBPCR1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define USBPCR1_REFCLKSEL_SHIFT	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define USBPCR1_REFCLKSEL_MASK	(0x3 << USBPCR1_REFCLKSEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define USBPCR1_REFCLKSEL_CORE	(0x2 << USBPCR1_REFCLKSEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define USBPCR1_REFCLKDIV_SHIFT	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define USBPCR1_REFCLKDIV_MASK	(0x3 << USBPCR1_REFCLKDIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define USBPCR1_REFCLKDIV_48	(0x2 << USBPCR1_REFCLKDIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define USBPCR1_REFCLKDIV_24	(0x1 << USBPCR1_REFCLKDIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define USBPCR1_REFCLKDIV_12	(0x0 << USBPCR1_REFCLKDIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static struct ingenic_cgu *cgu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static unsigned long x1000_otg_phy_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 						unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	u32 usbpcr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	unsigned refclk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	refclk_div = usbpcr1 & USBPCR1_REFCLKDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	switch (refclk_div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	case USBPCR1_REFCLKDIV_12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		return 12000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	case USBPCR1_REFCLKDIV_24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		return 24000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	case USBPCR1_REFCLKDIV_48:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		return 48000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static long x1000_otg_phy_round_rate(struct clk_hw *hw, unsigned long req_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 				      unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	if (req_rate < 18000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		return 12000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	if (req_rate < 36000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		return 24000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	return 48000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static int x1000_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 				   unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	u32 usbpcr1, div_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	switch (req_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	case 12000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		div_bits = USBPCR1_REFCLKDIV_12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	case 24000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		div_bits = USBPCR1_REFCLKDIV_24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	case 48000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		div_bits = USBPCR1_REFCLKDIV_48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	spin_lock_irqsave(&cgu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	usbpcr1 &= ~USBPCR1_REFCLKDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	usbpcr1 |= div_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	writel(usbpcr1, cgu->base + CGU_REG_USBPCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	spin_unlock_irqrestore(&cgu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int x1000_usb_phy_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	void __iomem *reg_opcr		= cgu->base + CGU_REG_OPCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	void __iomem *reg_usbpcr	= cgu->base + CGU_REG_USBPCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	writel(readl(reg_opcr) | OPCR_SPENDN0, reg_opcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	writel(readl(reg_usbpcr) & ~USBPCR_OTG_DISABLE & ~USBPCR_SIDDQ, reg_usbpcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void x1000_usb_phy_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	void __iomem *reg_opcr		= cgu->base + CGU_REG_OPCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	void __iomem *reg_usbpcr	= cgu->base + CGU_REG_USBPCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	writel(readl(reg_opcr) & ~OPCR_SPENDN0, reg_opcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	writel(readl(reg_usbpcr) | USBPCR_OTG_DISABLE | USBPCR_SIDDQ, reg_usbpcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int x1000_usb_phy_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	void __iomem *reg_opcr		= cgu->base + CGU_REG_OPCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	void __iomem *reg_usbpcr	= cgu->base + CGU_REG_USBPCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	return (readl(reg_opcr) & OPCR_SPENDN0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		!(readl(reg_usbpcr) & USBPCR_SIDDQ) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		!(readl(reg_usbpcr) & USBPCR_OTG_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const struct clk_ops x1000_otg_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	.recalc_rate = x1000_otg_phy_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	.round_rate = x1000_otg_phy_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	.set_rate = x1000_otg_phy_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.enable		= x1000_usb_phy_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	.disable	= x1000_usb_phy_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	.is_enabled	= x1000_usb_phy_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const s8 pll_od_encoding[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	/* External clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	[X1000_CLK_EXCLK] = { "ext", CGU_CLK_EXT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	[X1000_CLK_RTCLK] = { "rtc", CGU_CLK_EXT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	/* PLLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	[X1000_CLK_APLL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		"apll", CGU_CLK_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		.pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			.reg = CGU_REG_APLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			.rate_multiplier = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			.m_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			.m_bits = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			.m_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			.n_shift = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			.n_bits = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			.n_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			.od_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			.od_bits = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			.od_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			.od_encoding = pll_od_encoding,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			.bypass_reg = CGU_REG_APLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 			.bypass_bit = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			.enable_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			.stable_bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	[X1000_CLK_MPLL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		"mpll", CGU_CLK_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		.pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			.reg = CGU_REG_MPLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			.rate_multiplier = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			.m_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			.m_bits = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			.m_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			.n_shift = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			.n_bits = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			.n_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			.od_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 			.od_bits = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			.od_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			.od_encoding = pll_od_encoding,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			.bypass_reg = CGU_REG_MPLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			.bypass_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			.enable_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			.stable_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	/* Custom (SoC-specific) OTG PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	[X1000_CLK_OTGPHY] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		"otg_phy", CGU_CLK_CUSTOM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		.parents = { -1, -1, X1000_CLK_EXCLK, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		.custom = { &x1000_otg_phy_ops },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	/* Muxes & dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	[X1000_CLK_SCLKA] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		"sclk_a", CGU_CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		.parents = { -1, X1000_CLK_EXCLK, X1000_CLK_APLL, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		.mux = { CGU_REG_CPCCR, 30, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	[X1000_CLK_CPUMUX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		"cpu_mux", CGU_CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		.mux = { CGU_REG_CPCCR, 28, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	[X1000_CLK_CPU] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		"cpu", CGU_CLK_DIV | CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		.parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		.div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		.gate = { CGU_REG_CLKGR, 30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	[X1000_CLK_L2CACHE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		"l2cache", CGU_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		.parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		.div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	[X1000_CLK_AHB0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		"ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		.mux = { CGU_REG_CPCCR, 26, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		.div = { CGU_REG_CPCCR, 8, 1, 4, 21, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	[X1000_CLK_AHB2PMUX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		"ahb2_apb_mux", CGU_CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		.mux = { CGU_REG_CPCCR, 24, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	[X1000_CLK_AHB2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		"ahb2", CGU_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		.parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		.div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	[X1000_CLK_PCLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		"pclk", CGU_CLK_DIV | CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		.parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		.div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		.gate = { CGU_REG_CLKGR, 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	[X1000_CLK_DDR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		"ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		.mux = { CGU_REG_DDRCDR, 30, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		.div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		.gate = { CGU_REG_CLKGR, 31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	[X1000_CLK_MAC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		"mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		.parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		.mux = { CGU_REG_MACCDR, 31, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		.div = { CGU_REG_MACCDR, 0, 1, 8, 29, 28, 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		.gate = { CGU_REG_CLKGR, 25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	[X1000_CLK_LCD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		"lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		.parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		.mux = { CGU_REG_LPCDR, 31, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		.div = { CGU_REG_LPCDR, 0, 1, 8, 28, 27, 26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		.gate = { CGU_REG_CLKGR, 23 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	[X1000_CLK_MSCMUX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		"msc_mux", CGU_CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		.parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		.mux = { CGU_REG_MSC0CDR, 31, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	[X1000_CLK_MSC0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		"msc0", CGU_CLK_DIV | CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		.parents = { X1000_CLK_MSCMUX, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		.div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		.gate = { CGU_REG_CLKGR, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	[X1000_CLK_MSC1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		"msc1", CGU_CLK_DIV | CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		.parents = { X1000_CLK_MSCMUX, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		.div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		.gate = { CGU_REG_CLKGR, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	[X1000_CLK_OTG] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		"otg", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		.parents = { X1000_CLK_EXCLK, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 					 X1000_CLK_APLL, X1000_CLK_MPLL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		.mux = { CGU_REG_USBCDR, 30, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		.div = { CGU_REG_USBCDR, 0, 1, 8, 29, 28, 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		.gate = { CGU_REG_CLKGR, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	[X1000_CLK_SSIPLL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		"ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		.parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		.mux = { CGU_REG_SSICDR, 31, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		.div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	[X1000_CLK_SSIPLL_DIV2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		"ssi_pll_div2", CGU_CLK_FIXDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		.parents = { X1000_CLK_SSIPLL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		.fixdiv = { 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	[X1000_CLK_SSIMUX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		"ssi_mux", CGU_CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		.parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL_DIV2, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		.mux = { CGU_REG_SSICDR, 30, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	[X1000_CLK_EXCLK_DIV512] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		"exclk_div512", CGU_CLK_FIXDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		.parents = { X1000_CLK_EXCLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		.fixdiv = { 512 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	[X1000_CLK_RTC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		"rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		.parents = { X1000_CLK_EXCLK_DIV512, X1000_CLK_RTCLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		.mux = { CGU_REG_OPCR, 2, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		.gate = { CGU_REG_CLKGR, 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	/* Gate-only clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	[X1000_CLK_EMC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		"emc", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		.parents = { X1000_CLK_AHB2, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		.gate = { CGU_REG_CLKGR, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	[X1000_CLK_EFUSE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		"efuse", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		.parents = { X1000_CLK_AHB2, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		.gate = { CGU_REG_CLKGR, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	[X1000_CLK_SFC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		"sfc", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		.parents = { X1000_CLK_SSIPLL, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		.gate = { CGU_REG_CLKGR, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	[X1000_CLK_I2C0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		"i2c0", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		.parents = { X1000_CLK_PCLK, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		.gate = { CGU_REG_CLKGR, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	[X1000_CLK_I2C1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		"i2c1", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		.parents = { X1000_CLK_PCLK, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		.gate = { CGU_REG_CLKGR, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	[X1000_CLK_I2C2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		"i2c2", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		.parents = { X1000_CLK_PCLK, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		.gate = { CGU_REG_CLKGR, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	[X1000_CLK_UART0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		"uart0", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		.gate = { CGU_REG_CLKGR, 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	[X1000_CLK_UART1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		"uart1", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		.gate = { CGU_REG_CLKGR, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	[X1000_CLK_UART2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		"uart2", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		.gate = { CGU_REG_CLKGR, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	[X1000_CLK_TCU] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		"tcu", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		.gate = { CGU_REG_CLKGR, 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	[X1000_CLK_SSI] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 		"ssi", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 		.parents = { X1000_CLK_SSIMUX, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		.gate = { CGU_REG_CLKGR, 19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	[X1000_CLK_OST] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		"ost", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 		.gate = { CGU_REG_CLKGR, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	[X1000_CLK_PDMA] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 		"pdma", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 		.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 		.gate = { CGU_REG_CLKGR, 21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static void __init x1000_cgu_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	cgu = ingenic_cgu_new(x1000_cgu_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 			      ARRAY_SIZE(x1000_cgu_clocks), np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	if (!cgu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 		pr_err("%s: failed to initialise CGU\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	retval = ingenic_cgu_register_clocks(cgu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 		pr_err("%s: failed to register CGU Clocks\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	ingenic_cgu_register_syscore_ops(cgu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)  * CGU has some children devices, this is useful for probing children devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)  * in the case where the device node is compatible with "simple-mfd".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) CLK_OF_DECLARE_DRIVER(x1000_cgu, "ingenic,x1000-cgu", x1000_cgu_init);