Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * JZ47xx SoCs TCU clocks driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2019 Paul Cercueil <paul@crapouillou.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/mfd/ingenic-tcu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <dt-bindings/clock/ingenic,tcu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /* 8 channels max + watchdog + OST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define TCU_CLK_COUNT	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #undef pr_fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define pr_fmt(fmt) "ingenic-tcu-clk: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) enum tcu_clk_parent {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	TCU_PARENT_PCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	TCU_PARENT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	TCU_PARENT_EXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) struct ingenic_soc_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	unsigned int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	bool has_ost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	bool has_tcu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) struct ingenic_tcu_clk_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct clk_init_data init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	u8 gate_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	u8 tcsr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) struct ingenic_tcu_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct ingenic_tcu *tcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	const struct ingenic_tcu_clk_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) struct ingenic_tcu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	const struct ingenic_soc_info *soc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct clk_hw_onecell_data *clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static struct ingenic_tcu *ingenic_tcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static inline struct ingenic_tcu_clk *to_tcu_clk(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	return container_of(hw, struct ingenic_tcu_clk, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static int ingenic_tcu_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	const struct ingenic_tcu_clk_info *info = tcu_clk->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct ingenic_tcu *tcu = tcu_clk->tcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	regmap_write(tcu->map, TCU_REG_TSCR, BIT(info->gate_bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static void ingenic_tcu_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	const struct ingenic_tcu_clk_info *info = tcu_clk->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	struct ingenic_tcu *tcu = tcu_clk->tcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	regmap_write(tcu->map, TCU_REG_TSSR, BIT(info->gate_bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static int ingenic_tcu_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	const struct ingenic_tcu_clk_info *info = tcu_clk->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	regmap_read(tcu_clk->tcu->map, TCU_REG_TSR, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	return !(value & BIT(info->gate_bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static bool ingenic_tcu_enable_regs(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	const struct ingenic_tcu_clk_info *info = tcu_clk->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	struct ingenic_tcu *tcu = tcu_clk->tcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	bool enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	 * If the SoC has no global TCU clock, we must ungate the channel's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	 * clock to be able to access its registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	 * If we have a TCU clock, it will be enabled automatically as it has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	 * been attached to the regmap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	if (!tcu->clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		enabled = !!ingenic_tcu_is_enabled(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		regmap_write(tcu->map, TCU_REG_TSCR, BIT(info->gate_bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	return enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void ingenic_tcu_disable_regs(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	const struct ingenic_tcu_clk_info *info = tcu_clk->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	struct ingenic_tcu *tcu = tcu_clk->tcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (!tcu->clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		regmap_write(tcu->map, TCU_REG_TSSR, BIT(info->gate_bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static u8 ingenic_tcu_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	const struct ingenic_tcu_clk_info *info = tcu_clk->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	ret = regmap_read(tcu_clk->tcu->map, info->tcsr_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	WARN_ONCE(ret < 0, "Unable to read TCSR %d", tcu_clk->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	return ffs(val & TCU_TCSR_PARENT_CLOCK_MASK) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int ingenic_tcu_set_parent(struct clk_hw *hw, u8 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	const struct ingenic_tcu_clk_info *info = tcu_clk->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	bool was_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	was_enabled = ingenic_tcu_enable_regs(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	ret = regmap_update_bits(tcu_clk->tcu->map, info->tcsr_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 				 TCU_TCSR_PARENT_CLOCK_MASK, BIT(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	WARN_ONCE(ret < 0, "Unable to update TCSR %d", tcu_clk->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (!was_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		ingenic_tcu_disable_regs(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static unsigned long ingenic_tcu_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	const struct ingenic_tcu_clk_info *info = tcu_clk->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	unsigned int prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	ret = regmap_read(tcu_clk->tcu->map, info->tcsr_reg, &prescale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	WARN_ONCE(ret < 0, "Unable to read TCSR %d", tcu_clk->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	prescale = (prescale & TCU_TCSR_PRESCALE_MASK) >> TCU_TCSR_PRESCALE_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	return parent_rate >> (prescale * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static u8 ingenic_tcu_get_prescale(unsigned long rate, unsigned long req_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	u8 prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	for (prescale = 0; prescale < 5; prescale++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		if ((rate >> (prescale * 2)) <= req_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			return prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	return 5; /* /1024 divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static long ingenic_tcu_round_rate(struct clk_hw *hw, unsigned long req_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	unsigned long rate = *parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	u8 prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (req_rate > rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	prescale = ingenic_tcu_get_prescale(rate, req_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	return rate >> (prescale * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int ingenic_tcu_set_rate(struct clk_hw *hw, unsigned long req_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	const struct ingenic_tcu_clk_info *info = tcu_clk->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	u8 prescale = ingenic_tcu_get_prescale(parent_rate, req_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	bool was_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	was_enabled = ingenic_tcu_enable_regs(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	ret = regmap_update_bits(tcu_clk->tcu->map, info->tcsr_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 				 TCU_TCSR_PRESCALE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 				 prescale << TCU_TCSR_PRESCALE_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	WARN_ONCE(ret < 0, "Unable to update TCSR %d", tcu_clk->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (!was_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		ingenic_tcu_disable_regs(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const struct clk_ops ingenic_tcu_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	.get_parent	= ingenic_tcu_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	.set_parent	= ingenic_tcu_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	.recalc_rate	= ingenic_tcu_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	.round_rate	= ingenic_tcu_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	.set_rate	= ingenic_tcu_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	.enable		= ingenic_tcu_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	.disable	= ingenic_tcu_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	.is_enabled	= ingenic_tcu_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const char * const ingenic_tcu_timer_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	[TCU_PARENT_PCLK] = "pclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	[TCU_PARENT_RTC]  = "rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	[TCU_PARENT_EXT]  = "ext",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define DEF_TIMER(_name, _gate_bit, _tcsr)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	{								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		.init_data = {						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			.name = _name,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			.parent_names = ingenic_tcu_timer_parents,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			.num_parents = ARRAY_SIZE(ingenic_tcu_timer_parents),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			.ops = &ingenic_tcu_clk_ops,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			.flags = CLK_SET_RATE_UNGATE,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		},							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		.gate_bit = _gate_bit,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		.tcsr_reg = _tcsr,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const struct ingenic_tcu_clk_info ingenic_tcu_clk_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	[TCU_CLK_TIMER0] = DEF_TIMER("timer0", 0, TCU_REG_TCSRc(0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	[TCU_CLK_TIMER1] = DEF_TIMER("timer1", 1, TCU_REG_TCSRc(1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	[TCU_CLK_TIMER2] = DEF_TIMER("timer2", 2, TCU_REG_TCSRc(2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	[TCU_CLK_TIMER3] = DEF_TIMER("timer3", 3, TCU_REG_TCSRc(3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	[TCU_CLK_TIMER4] = DEF_TIMER("timer4", 4, TCU_REG_TCSRc(4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	[TCU_CLK_TIMER5] = DEF_TIMER("timer5", 5, TCU_REG_TCSRc(5)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	[TCU_CLK_TIMER6] = DEF_TIMER("timer6", 6, TCU_REG_TCSRc(6)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	[TCU_CLK_TIMER7] = DEF_TIMER("timer7", 7, TCU_REG_TCSRc(7)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const struct ingenic_tcu_clk_info ingenic_tcu_watchdog_clk_info =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 					 DEF_TIMER("wdt", 16, TCU_REG_WDT_TCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const struct ingenic_tcu_clk_info ingenic_tcu_ost_clk_info =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 					 DEF_TIMER("ost", 15, TCU_REG_OST_TCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #undef DEF_TIMER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int __init ingenic_tcu_register_clock(struct ingenic_tcu *tcu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 			unsigned int idx, enum tcu_clk_parent parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			const struct ingenic_tcu_clk_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 			struct clk_hw_onecell_data *clocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	struct ingenic_tcu_clk *tcu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	tcu_clk = kzalloc(sizeof(*tcu_clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if (!tcu_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	tcu_clk->hw.init = &info->init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	tcu_clk->idx = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	tcu_clk->info = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	tcu_clk->tcu = tcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	/* Reset channel and clock divider, set default parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	ingenic_tcu_enable_regs(&tcu_clk->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	regmap_update_bits(tcu->map, info->tcsr_reg, 0xffff, BIT(parent));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	ingenic_tcu_disable_regs(&tcu_clk->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	err = clk_hw_register(NULL, &tcu_clk->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		kfree(tcu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	clocks->hws[idx] = &tcu_clk->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const struct ingenic_soc_info jz4740_soc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	.num_channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	.has_ost = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	.has_tcu_clk = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static const struct ingenic_soc_info jz4725b_soc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	.num_channels = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	.has_ost = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	.has_tcu_clk = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static const struct ingenic_soc_info jz4770_soc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	.num_channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	.has_ost = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	.has_tcu_clk = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const struct ingenic_soc_info x1000_soc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	.num_channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	.has_ost = false, /* X1000 has OST, but it not belong TCU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	.has_tcu_clk = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const struct of_device_id __maybe_unused ingenic_tcu_of_match[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	{ .compatible = "ingenic,jz4740-tcu", .data = &jz4740_soc_info, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	{ .compatible = "ingenic,jz4725b-tcu", .data = &jz4725b_soc_info, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	{ .compatible = "ingenic,jz4770-tcu", .data = &jz4770_soc_info, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	{ .compatible = "ingenic,x1000-tcu", .data = &x1000_soc_info, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int __init ingenic_tcu_probe(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	const struct of_device_id *id = of_match_node(ingenic_tcu_of_match, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	struct ingenic_tcu *tcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	map = device_node_to_regmap(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	if (IS_ERR(map))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		return PTR_ERR(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	tcu = kzalloc(sizeof(*tcu), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	if (!tcu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	tcu->map = map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	tcu->soc_info = id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	if (tcu->soc_info->has_tcu_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		tcu->clk = of_clk_get_by_name(np, "tcu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		if (IS_ERR(tcu->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 			ret = PTR_ERR(tcu->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 			pr_crit("Cannot get TCU clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 			goto err_free_tcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		ret = clk_prepare_enable(tcu->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 			pr_crit("Unable to enable TCU clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 			goto err_put_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	tcu->clocks = kzalloc(struct_size(tcu->clocks, hws, TCU_CLK_COUNT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 			      GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	if (!tcu->clocks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	tcu->clocks->num = TCU_CLK_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	for (i = 0; i < tcu->soc_info->num_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		ret = ingenic_tcu_register_clock(tcu, i, TCU_PARENT_EXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 						 &ingenic_tcu_clk_info[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 						 tcu->clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 			pr_crit("cannot register clock %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 			goto err_unregister_timer_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	 * We set EXT as the default parent clock for all the TCU clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	 * except for the watchdog one, where we set the RTC clock as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	 * parent. Since the EXT and PCLK are much faster than the RTC clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	 * the watchdog would kick after a maximum time of 5s, and we might
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	 * want a slower kicking time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	ret = ingenic_tcu_register_clock(tcu, TCU_CLK_WDT, TCU_PARENT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 					 &ingenic_tcu_watchdog_clk_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 					 tcu->clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		pr_crit("cannot register watchdog clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		goto err_unregister_timer_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	if (tcu->soc_info->has_ost) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		ret = ingenic_tcu_register_clock(tcu, TCU_CLK_OST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 						 TCU_PARENT_EXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 						 &ingenic_tcu_ost_clk_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 						 tcu->clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 			pr_crit("cannot register ost clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 			goto err_unregister_watchdog_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, tcu->clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		pr_crit("cannot add OF clock provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		goto err_unregister_ost_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	ingenic_tcu = tcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) err_unregister_ost_clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	if (tcu->soc_info->has_ost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		clk_hw_unregister(tcu->clocks->hws[i + 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) err_unregister_watchdog_clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	clk_hw_unregister(tcu->clocks->hws[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) err_unregister_timer_clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	for (i = 0; i < tcu->clocks->num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		if (tcu->clocks->hws[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 			clk_hw_unregister(tcu->clocks->hws[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	kfree(tcu->clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) err_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	if (tcu->soc_info->has_tcu_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		clk_disable_unprepare(tcu->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) err_put_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	if (tcu->soc_info->has_tcu_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 		clk_put(tcu->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) err_free_tcu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	kfree(tcu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static int __maybe_unused tcu_pm_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	struct ingenic_tcu *tcu = ingenic_tcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	if (tcu->clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 		clk_disable(tcu->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static void __maybe_unused tcu_pm_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	struct ingenic_tcu *tcu = ingenic_tcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	if (tcu->clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		clk_enable(tcu->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static struct syscore_ops __maybe_unused tcu_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	.suspend = tcu_pm_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	.resume = tcu_pm_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static void __init ingenic_tcu_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	int ret = ingenic_tcu_probe(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 		pr_crit("Failed to initialize TCU clocks: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	if (IS_ENABLED(CONFIG_PM_SLEEP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 		register_syscore_ops(&tcu_pm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-tcu", ingenic_tcu_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) CLK_OF_DECLARE_DRIVER(jz4725b_cgu, "ingenic,jz4725b-tcu", ingenic_tcu_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) CLK_OF_DECLARE_DRIVER(jz4770_cgu, "ingenic,jz4770-tcu", ingenic_tcu_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) CLK_OF_DECLARE_DRIVER(x1000_cgu, "ingenic,x1000-tcu", ingenic_tcu_init);