Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * JZ4770 SoC CGU driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright 2018, Paul Cercueil <paul@crapouillou.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <dt-bindings/clock/jz4770-cgu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "cgu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * CPM registers offset address definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define CGU_REG_CPCCR		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CGU_REG_LCR		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CGU_REG_CPPCR0		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CGU_REG_CLKGR0		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CGU_REG_OPCR		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CGU_REG_CLKGR1		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CGU_REG_CPPCR1		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CGU_REG_USBPCR1		0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CGU_REG_USBCDR		0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define CGU_REG_I2SCDR		0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CGU_REG_LPCDR		0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CGU_REG_MSC0CDR		0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define CGU_REG_UHCCDR		0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define CGU_REG_SSICDR		0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define CGU_REG_CIMCDR		0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CGU_REG_GPSCDR		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CGU_REG_PCMCDR		0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CGU_REG_GPUCDR		0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CGU_REG_MSC1CDR		0xA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define CGU_REG_MSC2CDR		0xA8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define CGU_REG_BCHCDR		0xAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /* bits within the OPCR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define OPCR_SPENDH		BIT(5)		/* UHC PHY suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /* bits within the USBPCR1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define USBPCR1_UHC_POWER	BIT(5)		/* UHC PHY power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static struct ingenic_cgu *cgu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static int jz4770_uhc_phy_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	void __iomem *reg_opcr		= cgu->base + CGU_REG_OPCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	void __iomem *reg_usbpcr1	= cgu->base + CGU_REG_USBPCR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	writel(readl(reg_opcr) & ~OPCR_SPENDH, reg_opcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	writel(readl(reg_usbpcr1) | USBPCR1_UHC_POWER, reg_usbpcr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static void jz4770_uhc_phy_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	void __iomem *reg_opcr		= cgu->base + CGU_REG_OPCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	void __iomem *reg_usbpcr1	= cgu->base + CGU_REG_USBPCR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	writel(readl(reg_usbpcr1) & ~USBPCR1_UHC_POWER, reg_usbpcr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	writel(readl(reg_opcr) | OPCR_SPENDH, reg_opcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static int jz4770_uhc_phy_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	void __iomem *reg_opcr		= cgu->base + CGU_REG_OPCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	void __iomem *reg_usbpcr1	= cgu->base + CGU_REG_USBPCR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	return !(readl(reg_opcr) & OPCR_SPENDH) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		(readl(reg_usbpcr1) & USBPCR1_UHC_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static const struct clk_ops jz4770_uhc_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	.enable = jz4770_uhc_phy_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	.disable = jz4770_uhc_phy_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	.is_enabled = jz4770_uhc_phy_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static const s8 pll_od_encoding[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static const u8 jz4770_cgu_cpccr_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	1, 2, 3, 4, 6, 8, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	/* External clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	[JZ4770_CLK_EXT] = { "ext", CGU_CLK_EXT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	[JZ4770_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	/* PLLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	[JZ4770_CLK_PLL0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		"pll0", CGU_CLK_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		.parents = { JZ4770_CLK_EXT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		.pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			.reg = CGU_REG_CPPCR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 			.rate_multiplier = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			.m_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			.m_bits = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			.m_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			.n_shift = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			.n_bits = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			.n_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 			.od_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			.od_bits = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			.od_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			.od_encoding = pll_od_encoding,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			.bypass_reg = CGU_REG_CPPCR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			.bypass_bit = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			.enable_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			.stable_bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	[JZ4770_CLK_PLL1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		/* TODO: PLL1 can depend on PLL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		"pll1", CGU_CLK_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		.parents = { JZ4770_CLK_EXT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		.pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			.reg = CGU_REG_CPPCR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			.rate_multiplier = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			.m_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			.m_bits = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			.m_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			.n_shift = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			.n_bits = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			.n_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			.od_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			.od_bits = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			.od_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			.od_encoding = pll_od_encoding,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			.bypass_reg = CGU_REG_CPPCR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			.no_bypass_bit = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			.enable_bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			.stable_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	/* Main clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	[JZ4770_CLK_CCLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		"cclk", CGU_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		.parents = { JZ4770_CLK_PLL0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		.div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			jz4770_cgu_cpccr_div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	[JZ4770_CLK_H0CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		"h0clk", CGU_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		.parents = { JZ4770_CLK_PLL0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		.div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			jz4770_cgu_cpccr_div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	[JZ4770_CLK_H1CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		"h1clk", CGU_CLK_DIV | CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		.parents = { JZ4770_CLK_PLL0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		.div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			jz4770_cgu_cpccr_div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		.gate = { CGU_REG_CLKGR1, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	[JZ4770_CLK_H2CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		"h2clk", CGU_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		.parents = { JZ4770_CLK_PLL0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		.div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			jz4770_cgu_cpccr_div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	[JZ4770_CLK_C1CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		"c1clk", CGU_CLK_DIV | CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		.parents = { JZ4770_CLK_PLL0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		.div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			jz4770_cgu_cpccr_div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		.gate = { CGU_REG_OPCR, 31, true }, // disable CCLK stop on idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	[JZ4770_CLK_PCLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		"pclk", CGU_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		.parents = { JZ4770_CLK_PLL0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		.div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			jz4770_cgu_cpccr_div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	/* Those divided clocks can connect to PLL0 or PLL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	[JZ4770_CLK_MMC0_MUX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		"mmc0_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		.parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		.mux = { CGU_REG_MSC0CDR, 30, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		.div = { CGU_REG_MSC0CDR, 0, 1, 7, -1, -1, 31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		.gate = { CGU_REG_MSC0CDR, 31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	[JZ4770_CLK_MMC1_MUX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		"mmc1_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		.parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		.mux = { CGU_REG_MSC1CDR, 30, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		.div = { CGU_REG_MSC1CDR, 0, 1, 7, -1, -1, 31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		.gate = { CGU_REG_MSC1CDR, 31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	[JZ4770_CLK_MMC2_MUX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		"mmc2_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		.parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		.mux = { CGU_REG_MSC2CDR, 30, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		.div = { CGU_REG_MSC2CDR, 0, 1, 7, -1, -1, 31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		.gate = { CGU_REG_MSC2CDR, 31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	[JZ4770_CLK_CIM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		"cim", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		.parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		.mux = { CGU_REG_CIMCDR, 31, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		.div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		.gate = { CGU_REG_CLKGR0, 26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	[JZ4770_CLK_UHC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		"uhc", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		.parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		.mux = { CGU_REG_UHCCDR, 29, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		.div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		.gate = { CGU_REG_CLKGR0, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	[JZ4770_CLK_GPU] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		"gpu", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		.parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		.mux = { CGU_REG_GPUCDR, 31, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		.div = { CGU_REG_GPUCDR, 0, 1, 3, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		.gate = { CGU_REG_CLKGR1, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	[JZ4770_CLK_BCH] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		"bch", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		.parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		.mux = { CGU_REG_BCHCDR, 31, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		.div = { CGU_REG_BCHCDR, 0, 1, 3, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		.gate = { CGU_REG_CLKGR0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	[JZ4770_CLK_LPCLK_MUX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		"lpclk", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		.parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		.mux = { CGU_REG_LPCDR, 29, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		.div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		.gate = { CGU_REG_CLKGR0, 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	[JZ4770_CLK_GPS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		"gps", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		.parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		.mux = { CGU_REG_GPSCDR, 31, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		.div = { CGU_REG_GPSCDR, 0, 1, 4, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		.gate = { CGU_REG_CLKGR0, 22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	/* Those divided clocks can connect to EXT, PLL0 or PLL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	[JZ4770_CLK_SSI_MUX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		"ssi_mux", CGU_CLK_DIV | CGU_CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		.parents = { JZ4770_CLK_EXT, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		.mux = { CGU_REG_SSICDR, 30, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		.div = { CGU_REG_SSICDR, 0, 1, 6, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	[JZ4770_CLK_PCM_MUX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		"pcm_mux", CGU_CLK_DIV | CGU_CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		.parents = { JZ4770_CLK_EXT, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 			JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		.mux = { CGU_REG_PCMCDR, 30, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		.div = { CGU_REG_PCMCDR, 0, 1, 9, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	[JZ4770_CLK_I2S] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		"i2s", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		.parents = { JZ4770_CLK_EXT, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 			JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		.mux = { CGU_REG_I2SCDR, 30, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		.div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		.gate = { CGU_REG_CLKGR1, 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	[JZ4770_CLK_OTG] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		"usb", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		.parents = { JZ4770_CLK_EXT, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		.mux = { CGU_REG_USBCDR, 30, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		.div = { CGU_REG_USBCDR, 0, 1, 8, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		.gate = { CGU_REG_CLKGR0, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	/* Gate-only clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	[JZ4770_CLK_SSI0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		"ssi0", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		.parents = { JZ4770_CLK_SSI_MUX, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		.gate = { CGU_REG_CLKGR0, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	[JZ4770_CLK_SSI1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		"ssi1", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		.parents = { JZ4770_CLK_SSI_MUX, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		.gate = { CGU_REG_CLKGR0, 19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	[JZ4770_CLK_SSI2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		"ssi2", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		.parents = { JZ4770_CLK_SSI_MUX, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		.gate = { CGU_REG_CLKGR0, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	[JZ4770_CLK_PCM0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		"pcm0", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		.parents = { JZ4770_CLK_PCM_MUX, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		.gate = { CGU_REG_CLKGR1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	[JZ4770_CLK_PCM1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		"pcm1", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		.parents = { JZ4770_CLK_PCM_MUX, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		.gate = { CGU_REG_CLKGR1, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	[JZ4770_CLK_DMA] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		"dma", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		.parents = { JZ4770_CLK_H2CLK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		.gate = { CGU_REG_CLKGR0, 21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	[JZ4770_CLK_I2C0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		"i2c0", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		.parents = { JZ4770_CLK_EXT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		.gate = { CGU_REG_CLKGR0, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	[JZ4770_CLK_I2C1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		"i2c1", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		.parents = { JZ4770_CLK_EXT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		.gate = { CGU_REG_CLKGR0, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	[JZ4770_CLK_I2C2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		"i2c2", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		.parents = { JZ4770_CLK_EXT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		.gate = { CGU_REG_CLKGR1, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	[JZ4770_CLK_UART0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		"uart0", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		.parents = { JZ4770_CLK_EXT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		.gate = { CGU_REG_CLKGR0, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	[JZ4770_CLK_UART1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		"uart1", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		.parents = { JZ4770_CLK_EXT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		.gate = { CGU_REG_CLKGR0, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	[JZ4770_CLK_UART2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		"uart2", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		.parents = { JZ4770_CLK_EXT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		.gate = { CGU_REG_CLKGR0, 17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	[JZ4770_CLK_UART3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		"uart3", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		.parents = { JZ4770_CLK_EXT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		.gate = { CGU_REG_CLKGR0, 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	[JZ4770_CLK_IPU] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		"ipu", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		.parents = { JZ4770_CLK_H0CLK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		.gate = { CGU_REG_CLKGR0, 29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	[JZ4770_CLK_ADC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		"adc", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		.parents = { JZ4770_CLK_EXT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		.gate = { CGU_REG_CLKGR0, 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	[JZ4770_CLK_AIC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		"aic", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		.parents = { JZ4770_CLK_EXT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		.gate = { CGU_REG_CLKGR0, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	[JZ4770_CLK_AUX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		"aux", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		.parents = { JZ4770_CLK_C1CLK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		.gate = { CGU_REG_CLKGR1, 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	[JZ4770_CLK_VPU] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		"vpu", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		.parents = { JZ4770_CLK_H1CLK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		.gate = { CGU_REG_LCR, 30, false, 150 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	[JZ4770_CLK_MMC0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		"mmc0", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		.parents = { JZ4770_CLK_MMC0_MUX, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		.gate = { CGU_REG_CLKGR0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	[JZ4770_CLK_MMC1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		"mmc1", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		.parents = { JZ4770_CLK_MMC1_MUX, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		.gate = { CGU_REG_CLKGR0, 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	[JZ4770_CLK_MMC2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		"mmc2", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		.parents = { JZ4770_CLK_MMC2_MUX, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		.gate = { CGU_REG_CLKGR0, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	[JZ4770_CLK_OTG_PHY] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		"usb_phy", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		.parents = { JZ4770_CLK_OTG },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		.gate = { CGU_REG_OPCR, 7, true, 50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	/* Custom clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	[JZ4770_CLK_UHC_PHY] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		"uhc_phy", CGU_CLK_CUSTOM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		.parents = { JZ4770_CLK_UHC, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		.custom = { &jz4770_uhc_phy_ops },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	[JZ4770_CLK_EXT512] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		"ext/512", CGU_CLK_FIXDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		.parents = { JZ4770_CLK_EXT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		.fixdiv = { 512 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	[JZ4770_CLK_RTC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		"rtc", CGU_CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		.parents = { JZ4770_CLK_EXT512, JZ4770_CLK_OSC32K, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		.mux = { CGU_REG_OPCR, 2, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static void __init jz4770_cgu_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	cgu = ingenic_cgu_new(jz4770_cgu_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 			      ARRAY_SIZE(jz4770_cgu_clocks), np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	if (!cgu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 		pr_err("%s: failed to initialise CGU\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	retval = ingenic_cgu_register_clocks(cgu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 		pr_err("%s: failed to register CGU Clocks\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	ingenic_cgu_register_syscore_ops(cgu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* We only probe via devicetree, no need for a platform driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) CLK_OF_DECLARE_DRIVER(jz4770_cgu, "ingenic,jz4770-cgu", jz4770_cgu_init);