Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Ingenic JZ4725B SoC CGU driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2018 Paul Cercueil
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Paul Cercueil <paul@crapouillou.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <dt-bindings/clock/jz4725b-cgu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "cgu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /* CGU register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define CGU_REG_CPCCR		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define CGU_REG_LCR		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define CGU_REG_CPPCR		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CGU_REG_CLKGR		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CGU_REG_OPCR		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CGU_REG_I2SCDR		0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CGU_REG_LPCDR		0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CGU_REG_MSCCDR		0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CGU_REG_SSICDR		0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CGU_REG_CIMCDR		0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /* bits within the LCR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define LCR_SLEEP		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) static struct ingenic_cgu *cgu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static const s8 pll_od_encoding[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	0x0, 0x1, -1, 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) static const u8 jz4725b_cgu_cpccr_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	1, 2, 3, 4, 6, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static const u8 jz4725b_cgu_pll_half_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	2, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	/* External clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	[JZ4725B_CLK_EXT] = { "ext", CGU_CLK_EXT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	[JZ4725B_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	[JZ4725B_CLK_PLL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		"pll", CGU_CLK_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		.pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 			.reg = CGU_REG_CPPCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 			.rate_multiplier = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 			.m_shift = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 			.m_bits = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 			.m_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 			.n_shift = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 			.n_bits = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 			.n_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 			.od_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 			.od_bits = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 			.od_max = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			.od_encoding = pll_od_encoding,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 			.stable_bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			.bypass_reg = CGU_REG_CPPCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 			.bypass_bit = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 			.enable_bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	/* Muxes & dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	[JZ4725B_CLK_PLL_HALF] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		"pll half", CGU_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		.div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			jz4725b_cgu_pll_half_div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	[JZ4725B_CLK_CCLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		"cclk", CGU_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		.div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			jz4725b_cgu_cpccr_div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	[JZ4725B_CLK_HCLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		"hclk", CGU_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		.div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			jz4725b_cgu_cpccr_div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	[JZ4725B_CLK_PCLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		"pclk", CGU_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		.div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			jz4725b_cgu_cpccr_div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	[JZ4725B_CLK_MCLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		"mclk", CGU_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		.div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			jz4725b_cgu_cpccr_div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	[JZ4725B_CLK_IPU] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		"ipu", CGU_CLK_DIV | CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		.div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			jz4725b_cgu_cpccr_div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		.gate = { CGU_REG_CLKGR, 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	[JZ4725B_CLK_LCD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		"lcd", CGU_CLK_DIV | CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		.parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		.div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		.gate = { CGU_REG_CLKGR, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	[JZ4725B_CLK_I2S] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		"i2s", CGU_CLK_MUX | CGU_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		.parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		.mux = { CGU_REG_CPCCR, 31, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		.div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	[JZ4725B_CLK_SPI] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		"spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		.parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		.mux = { CGU_REG_SSICDR, 31, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		.div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		.gate = { CGU_REG_CLKGR, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	[JZ4725B_CLK_MMC_MUX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		"mmc_mux", CGU_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		.parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		.div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	[JZ4725B_CLK_UDC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		"udc", CGU_CLK_MUX | CGU_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		.parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		.mux = { CGU_REG_CPCCR, 29, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		.div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	/* Gate-only clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	[JZ4725B_CLK_UART] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		"uart", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		.gate = { CGU_REG_CLKGR, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	[JZ4725B_CLK_DMA] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		"dma", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		.parents = { JZ4725B_CLK_PCLK, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		.gate = { CGU_REG_CLKGR, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	[JZ4725B_CLK_ADC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		"adc", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		.gate = { CGU_REG_CLKGR, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	[JZ4725B_CLK_I2C] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		"i2c", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		.gate = { CGU_REG_CLKGR, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	[JZ4725B_CLK_AIC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		"aic", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		.gate = { CGU_REG_CLKGR, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	[JZ4725B_CLK_MMC0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		"mmc0", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		.parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		.gate = { CGU_REG_CLKGR, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	[JZ4725B_CLK_MMC1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		"mmc1", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		.parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		.gate = { CGU_REG_CLKGR, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	[JZ4725B_CLK_BCH] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		"bch", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		.parents = { JZ4725B_CLK_MCLK/* not sure */, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		.gate = { CGU_REG_CLKGR, 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	[JZ4725B_CLK_TCU] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		"tcu", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		.parents = { JZ4725B_CLK_EXT/* not sure */, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		.gate = { CGU_REG_CLKGR, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	[JZ4725B_CLK_EXT512] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		"ext/512", CGU_CLK_FIXDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		.parents = { JZ4725B_CLK_EXT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		/* Doc calls it EXT512, but it seems to be /256... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		.fixdiv = { 256 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	[JZ4725B_CLK_RTC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		"rtc", CGU_CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		.parents = { JZ4725B_CLK_EXT512, JZ4725B_CLK_OSC32K, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		.mux = { CGU_REG_OPCR, 2, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	[JZ4725B_CLK_UDC_PHY] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		"udc_phy", CGU_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		.gate = { CGU_REG_OPCR, 6, true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static void __init jz4725b_cgu_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	cgu = ingenic_cgu_new(jz4725b_cgu_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			      ARRAY_SIZE(jz4725b_cgu_clocks), np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (!cgu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		pr_err("%s: failed to initialise CGU\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	retval = ingenic_cgu_register_clocks(cgu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		pr_err("%s: failed to register CGU Clocks\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	ingenic_cgu_register_syscore_ops(cgu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) CLK_OF_DECLARE_DRIVER(jz4725b_cgu, "ingenic,jz4725b-cgu", jz4725b_cgu_init);