^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Ingenic SoC CGU driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2013-2015 Imagination Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Paul Burton <paul.burton@mips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __DRIVERS_CLK_INGENIC_CGU_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __DRIVERS_CLK_INGENIC_CGU_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * struct ingenic_cgu_pll_info - information about a PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * @reg: the offset of the PLL's control register within the CGU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * @rate_multiplier: the multiplier needed by pll rate calculation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * @m_shift: the number of bits to shift the multiplier value by (ie. the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * index of the lowest bit of the multiplier value in the PLL's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * control register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * @m_bits: the size of the multiplier field in bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * @m_offset: the multiplier value which encodes to 0 in the PLL's control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * @n_shift: the number of bits to shift the divider value by (ie. the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * index of the lowest bit of the divider value in the PLL's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * control register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * @n_bits: the size of the divider field in bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * @n_offset: the divider value which encodes to 0 in the PLL's control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @od_shift: the number of bits to shift the post-VCO divider value by (ie.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * the index of the lowest bit of the post-VCO divider value in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * the PLL's control register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * @od_bits: the size of the post-VCO divider field in bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * @od_max: the maximum post-VCO divider value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * @od_encoding: a pointer to an array mapping post-VCO divider values to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * their encoded values in the PLL control register, or -1 for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * unsupported values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @bypass_reg: the offset of the bypass control register within the CGU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @bypass_bit: the index of the bypass bit in the PLL control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @enable_bit: the index of the enable bit in the PLL control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @stable_bit: the index of the stable bit in the PLL control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @no_bypass_bit: if set, the PLL has no bypass functionality
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct ingenic_cgu_pll_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned rate_multiplier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) const s8 *od_encoding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u8 m_shift, m_bits, m_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u8 n_shift, n_bits, n_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u8 od_shift, od_bits, od_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned bypass_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u8 bypass_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u8 enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u8 stable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) bool no_bypass_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * struct ingenic_cgu_mux_info - information about a clock mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @reg: offset of the mux control register within the CGU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @shift: number of bits to shift the mux value by (ie. the index of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * the lowest bit of the mux value within its control register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @bits: the size of the mux value in bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct ingenic_cgu_mux_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u8 bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * struct ingenic_cgu_div_info - information about a divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @reg: offset of the divider control register within the CGU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @shift: number of bits to left shift the divide value by (ie. the index of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * the lowest bit of the divide value within its control register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @div: number to divide the divider value by (i.e. if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * effective divider value is the value written to the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * multiplied by some constant)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @bits: the size of the divide value in bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @ce_bit: the index of the change enable bit within reg, or -1 if there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * isn't one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @busy_bit: the index of the busy bit within reg, or -1 if there isn't one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @stop_bit: the index of the stop bit within reg, or -1 if there isn't one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * @div_table: optional table to map the value read from the register to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * actual divider value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct ingenic_cgu_div_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u8 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u8 bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) s8 ce_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) s8 busy_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) s8 stop_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) const u8 *div_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * struct ingenic_cgu_fixdiv_info - information about a fixed divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * @div: the divider applied to the parent clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct ingenic_cgu_fixdiv_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * struct ingenic_cgu_gate_info - information about a clock gate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * @reg: offset of the gate control register within the CGU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @bit: offset of the bit in the register that controls the gate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @clear_to_gate: if set, the clock is gated when the bit is cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @delay_us: delay in microseconds after which the clock is considered stable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct ingenic_cgu_gate_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u8 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) bool clear_to_gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u16 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * struct ingenic_cgu_custom_info - information about a custom (SoC) clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * @clk_ops: custom clock operation callbacks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct ingenic_cgu_custom_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) const struct clk_ops *clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * struct ingenic_cgu_clk_info - information about a clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @name: name of the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * @type: a bitmask formed from CGU_CLK_* values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * @parents: an array of the indices of potential parents of this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * within the clock_info array of the CGU, or -1 in entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * which correspond to no valid parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * @pll: information valid if type includes CGU_CLK_PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @gate: information valid if type includes CGU_CLK_GATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * @mux: information valid if type includes CGU_CLK_MUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * @div: information valid if type includes CGU_CLK_DIV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * @fixdiv: information valid if type includes CGU_CLK_FIXDIV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * @custom: information valid if type includes CGU_CLK_CUSTOM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct ingenic_cgu_clk_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) CGU_CLK_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) CGU_CLK_EXT = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) CGU_CLK_PLL = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) CGU_CLK_GATE = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) CGU_CLK_MUX = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) CGU_CLK_MUX_GLITCHFREE = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) CGU_CLK_DIV = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) CGU_CLK_FIXDIV = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) CGU_CLK_CUSTOM = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) } type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int parents[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct ingenic_cgu_pll_info pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct ingenic_cgu_gate_info gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct ingenic_cgu_mux_info mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct ingenic_cgu_div_info div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct ingenic_cgu_fixdiv_info fixdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct ingenic_cgu_custom_info custom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * struct ingenic_cgu - data about the CGU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * @np: the device tree node that caused the CGU to be probed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * @base: the ioremap'ed base address of the CGU registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * @clock_info: an array containing information about implemented clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * @clocks: used to provide clocks to DT, allows lookup of struct clk*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * @lock: lock to be held whilst manipulating CGU registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct ingenic_cgu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) const struct ingenic_cgu_clk_info *clock_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct clk_onecell_data clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * struct ingenic_clk - private data for a clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * @hw: see Documentation/driver-api/clk.rst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * @cgu: a pointer to the CGU data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * @idx: the index of this clock in cgu->clock_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct ingenic_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct ingenic_cgu *cgu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define to_ingenic_clk(_hw) container_of(_hw, struct ingenic_clk, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * ingenic_cgu_new() - create a new CGU instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * @clock_info: an array of clock information structures describing the clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * which are implemented by the CGU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * @num_clocks: the number of entries in clock_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * @np: the device tree node which causes this CGU to be probed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * Return: a pointer to the CGU instance if initialisation is successful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * otherwise NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct ingenic_cgu *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ingenic_cgu_new(const struct ingenic_cgu_clk_info *clock_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned num_clocks, struct device_node *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * ingenic_cgu_register_clocks() - Registers the clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * @cgu: pointer to cgu data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * Register the clocks described by the CGU with the common clock framework.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * Return: 0 on success or -errno if unsuccesful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #endif /* __DRIVERS_CLK_INGENIC_CGU_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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