^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __MACH_IMX_CLK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __MACH_IMX_CLK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define IMX_CLK_GATE2_SINGLE_BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) extern spinlock_t imx_ccm_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) void imx_check_clocks(struct clk *clks[], unsigned int count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) void imx_register_uart_clocks(unsigned int clk_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static inline void imx_register_uart_clocks(unsigned int clk_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) void imx_mmdc_mask_handshake(void __iomem *ccm_base, unsigned int chn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) void imx_unregister_clocks(struct clk *clks[], unsigned int count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) void imx_unregister_hw_clocks(struct clk_hw *hws[], unsigned int count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) extern void imx_cscmr1_fixup(u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) enum imx_pllv1_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) IMX_PLLV1_IMX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) IMX_PLLV1_IMX21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) IMX_PLLV1_IMX25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) IMX_PLLV1_IMX27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) IMX_PLLV1_IMX31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) IMX_PLLV1_IMX35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) enum imx_sscg_pll_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) SCCG_PLL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) SCCG_PLL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) enum imx_pll14xx_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) PLL_1416X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) PLL_1443X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* NOTE: Rate table should be kept sorted in descending order. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct imx_pll14xx_rate_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned int pdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned int mdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned int sdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned int kdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct imx_pll14xx_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) enum imx_pll14xx_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) const struct imx_pll14xx_rate_table *rate_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int rate_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) extern struct imx_pll14xx_clk imx_1416x_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) extern struct imx_pll14xx_clk imx_1443x_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) extern struct imx_pll14xx_clk imx_1443x_dram_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) cgr_val, clk_gate_flags, lock, share_count) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) cgr_val, clk_gate_flags, lock, share_count))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define imx_clk_pfd(name, parent_name, reg, idx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define imx_clk_fixed(name, rate) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) to_clk(imx_clk_hw_fixed(name, rate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define imx_clk_fixed_factor(name, parent, mult, div) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) to_clk(imx_clk_hw_fixed_factor(name, parent, mult, div))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define imx_clk_divider(name, parent, reg, shift, width) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define imx_clk_divider2(name, parent, reg, shift, width) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) to_clk(imx_clk_hw_divider2(name, parent, reg, shift, width))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define imx_clk_gate(name, parent, reg, shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) to_clk(imx_clk_hw_gate(name, parent, reg, shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define imx_clk_gate_dis(name, parent, reg, shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define imx_clk_gate2(name, parent, reg, shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) to_clk(imx_clk_hw_gate2(name, parent, reg, shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define imx_clk_gate2_flags(name, parent, reg, shift, flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define imx_clk_gate2_shared2(name, parent, reg, shift, share_count) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) to_clk(imx_clk_hw_gate2_shared2(name, parent, reg, shift, share_count))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define imx_clk_gate3(name, parent, reg, shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) to_clk(imx_clk_hw_gate3(name, parent, reg, shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define imx_clk_gate4(name, parent, reg, shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) to_clk(imx_clk_hw_gate4(name, parent, reg, shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define imx_clk_pllv1(type, name, parent, base) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) to_clk(imx_clk_hw_pllv1(type, name, parent, base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define imx_clk_pllv2(name, parent, base) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) to_clk(imx_clk_hw_pllv2(name, parent, base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define imx_clk_frac_pll(name, parent_name, base) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) to_clk(imx_clk_hw_frac_pll(name, parent_name, base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define imx_clk_sscg_pll(name, parent_names, num_parents, parent,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) bypass1, bypass2, base, flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) to_clk(imx_clk_hw_sscg_pll(name, parent_names, num_parents, parent,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) bypass1, bypass2, base, flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) void __iomem *base, const struct imx_pll14xx_clk *pll_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define imx_clk_pll14xx(name, parent_name, base, pll_clk) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) to_clk(imx_clk_hw_pll14xx(name, parent_name, base, pll_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) const char *parent_name, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) const struct imx_pll14xx_clk *pll_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) const char *parent, void __iomem *base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) void __iomem *base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) void __iomem *base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct clk_hw *imx_clk_hw_sscg_pll(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) const char * const *parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u8 num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u8 parent, u8 bypass1, u8 bypass2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) enum imx_pllv3_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) IMX_PLLV3_GENERIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) IMX_PLLV3_SYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) IMX_PLLV3_USB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) IMX_PLLV3_USB_VF610,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) IMX_PLLV3_AV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) IMX_PLLV3_ENET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) IMX_PLLV3_ENET_IMX7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) IMX_PLLV3_SYS_VF610,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) IMX_PLLV3_DDR_IMX7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) IMX_PLLV3_AV_IMX7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) const char *parent_name, void __iomem *base, u32 div_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define PLL_1416X_RATE(_rate, _m, _p, _s) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .rate = (_rate), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .mdiv = (_m), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .pdiv = (_p), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .sdiv = (_s), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .rate = (_rate), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .mdiv = (_m), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .pdiv = (_p), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .sdiv = (_s), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .kdiv = (_k), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct clk_hw *imx_clk_hw_pllv4(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) void __iomem *base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) const char *parent_name, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) void __iomem *reg, u8 bit_idx, u8 cgr_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u8 clk_gate_flags, spinlock_t *lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned int *share_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct clk * imx_obtain_fixed_clock(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) const char *name, unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct clk_hw *imx_obtain_fixed_clock_hw(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) const char *name, unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct clk_hw *imx_obtain_fixed_clk_hw(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) const char *name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) void __iomem *reg, u8 shift, u32 exclusive_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) void __iomem *reg, u8 idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct clk_hw *imx_clk_hw_pfdv2(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) void __iomem *reg, u8 idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) void __iomem *reg, u8 shift, u8 width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) void __iomem *busy_reg, u8 busy_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct clk_hw *imx_clk_hw_busy_mux(const char *name, void __iomem *reg, u8 shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u8 width, void __iomem *busy_reg, u8 busy_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) const char * const *parent_names, int num_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct clk_hw *imx7ulp_clk_hw_composite(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) const char * const *parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int num_parents, bool mux_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) bool rate_present, bool gate_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) void __iomem *reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct clk_hw *imx_clk_hw_fixup_divider(const char *name, const char *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) void __iomem *reg, u8 shift, u8 width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) void (*fixup)(u32 *val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct clk_hw *imx_clk_hw_fixup_mux(const char *name, void __iomem *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u8 shift, u8 width, const char * const *parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int num_parents, void (*fixup)(u32 *val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static inline struct clk *to_clk(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (IS_ERR_OR_NULL(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return ERR_CAST(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return hw->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static inline struct clk_hw *imx_clk_hw_pll14xx(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) const struct imx_pll14xx_clk *pll_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static inline struct clk_hw *imx_clk_hw_mux_ldb(const char *name, void __iomem *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u8 shift, u8 width, const char * const *parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int num_parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return clk_hw_register_mux(NULL, name, parents, num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) shift, width, CLK_MUX_READ_ONLY, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static inline struct clk_hw *imx_clk_hw_fixed_factor(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) const char *parent, unsigned int mult, unsigned int div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return clk_hw_register_fixed_factor(NULL, name, parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) CLK_SET_RATE_PARENT, mult, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static inline struct clk_hw *imx_clk_hw_divider(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) const char *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) void __iomem *reg, u8 shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u8 width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return clk_hw_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) reg, shift, width, 0, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static inline struct clk_hw *imx_clk_hw_divider_flags(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) const char *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) void __iomem *reg, u8 shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u8 width, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return clk_hw_register_divider(NULL, name, parent, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) reg, shift, width, 0, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static inline struct clk_hw *imx_clk_hw_divider2(const char *name, const char *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) void __iomem *reg, u8 shift, u8 width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return clk_hw_register_divider(NULL, name, parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) reg, shift, width, 0, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static inline struct clk *imx_clk_divider2_flags(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) const char *parent, void __iomem *reg, u8 shift, u8 width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return clk_register_divider(NULL, name, parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) reg, shift, width, 0, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static inline struct clk_hw *imx_clk_hw_gate_flags(const char *name, const char *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) void __iomem *reg, u8 shift, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) shift, 0, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static inline struct clk_hw *imx_clk_hw_gate(const char *name, const char *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) void __iomem *reg, u8 shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) shift, 0, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static inline struct clk_hw *imx_dev_clk_hw_gate(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) const char *parent, void __iomem *reg, u8 shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return clk_hw_register_gate(dev, name, parent, CLK_SET_RATE_PARENT, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) shift, 0, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static inline struct clk_hw *imx_clk_hw_gate_dis(const char *name, const char *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) void __iomem *reg, u8 shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static inline struct clk_hw *imx_clk_hw_gate_dis_flags(const char *name, const char *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) void __iomem *reg, u8 shift, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static inline struct clk_hw *imx_clk_hw_gate2(const char *name, const char *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) void __iomem *reg, u8 shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) shift, 0x3, 0, &imx_ccm_lock, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static inline struct clk_hw *imx_clk_hw_gate2_flags(const char *name, const char *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) void __iomem *reg, u8 shift, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return clk_hw_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) shift, 0x3, 0, &imx_ccm_lock, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static inline struct clk_hw *imx_clk_hw_gate2_shared(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) const char *parent, void __iomem *reg, u8 shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned int *share_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) shift, 0x3, 0, &imx_ccm_lock, share_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static inline struct clk_hw *imx_clk_hw_gate2_shared2(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) const char *parent, void __iomem *reg, u8 shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) unsigned int *share_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) &imx_ccm_lock, share_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static inline struct clk_hw *imx_dev_clk_hw_gate_shared(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) const char *name, const char *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) void __iomem *reg, u8 shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) unsigned int *share_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) CLK_OPS_PARENT_ENABLE, reg, shift, 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) IMX_CLK_GATE2_SINGLE_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) &imx_ccm_lock, share_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static inline struct clk *imx_clk_gate2_cgr(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) const char *parent, void __iomem *reg, u8 shift, u8 cgr_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) shift, cgr_val, 0, &imx_ccm_lock, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static inline struct clk_hw *imx_clk_hw_gate3(const char *name, const char *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) void __iomem *reg, u8 shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return clk_hw_register_gate(NULL, name, parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) reg, shift, 0, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static inline struct clk_hw *imx_clk_hw_gate3_flags(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) const char *parent, void __iomem *reg, u8 shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return clk_hw_register_gate(NULL, name, parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) reg, shift, 0, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define imx_clk_gate3_flags(name, parent, reg, shift, flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) to_clk(imx_clk_hw_gate3_flags(name, parent, reg, shift, flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static inline struct clk_hw *imx_clk_hw_gate4(const char *name, const char *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) void __iomem *reg, u8 shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return clk_hw_register_gate2(NULL, name, parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) reg, shift, 0x3, 0, &imx_ccm_lock, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static inline struct clk_hw *imx_clk_hw_gate4_flags(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) const char *parent, void __iomem *reg, u8 shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return clk_hw_register_gate2(NULL, name, parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) reg, shift, 0x3, 0, &imx_ccm_lock, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define imx_clk_gate4_flags(name, parent, reg, shift, flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) to_clk(imx_clk_hw_gate4_flags(name, parent, reg, shift, flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static inline struct clk_hw *imx_clk_hw_mux(const char *name, void __iomem *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) u8 shift, u8 width, const char * const *parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int num_parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return clk_hw_register_mux(NULL, name, parents, num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) CLK_SET_RATE_NO_REPARENT, reg, shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) width, 0, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static inline struct clk_hw *imx_dev_clk_hw_mux(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) const char *name, void __iomem *reg, u8 shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u8 width, const char * const *parents, int num_parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return clk_hw_register_mux(dev, name, parents, num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) CLK_SET_RATE_NO_REPARENT | CLK_SET_PARENT_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) reg, shift, width, 0, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u8 shift, u8 width, const char * const *parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) int num_parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return clk_register_mux(NULL, name, parents, num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) reg, shift, width, 0, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static inline struct clk_hw *imx_clk_hw_mux2(const char *name, void __iomem *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u8 shift, u8 width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) const char * const *parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) int num_parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return clk_hw_register_mux(NULL, name, parents, num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) CLK_SET_RATE_NO_REPARENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) CLK_OPS_PARENT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) reg, shift, width, 0, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static inline struct clk *imx_clk_mux_flags(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) void __iomem *reg, u8 shift, u8 width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) const char * const *parents, int num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return clk_register_mux(NULL, name, parents, num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static inline struct clk_hw *imx_clk_hw_mux2_flags(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) void __iomem *reg, u8 shift, u8 width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) const char * const *parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int num_parents, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return clk_hw_register_mux(NULL, name, parents, num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) reg, shift, width, 0, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static inline struct clk *imx_clk_mux2_flags(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) void __iomem *reg, u8 shift, u8 width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) const char * const *parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) int num_parents, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return clk_register_mux(NULL, name, parents, num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) reg, shift, width, 0, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static inline struct clk_hw *imx_clk_hw_mux_flags(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) void __iomem *reg, u8 shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u8 width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) const char * const *parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) int num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return clk_hw_register_mux(NULL, name, parents, num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) flags | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) reg, shift, width, 0, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static inline struct clk_hw *imx_dev_clk_hw_mux_flags(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) void __iomem *reg, u8 shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u8 width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) const char * const *parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) int num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return clk_hw_register_mux(dev, name, parents, num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) flags | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) reg, shift, width, 0, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct clk *div, struct clk *mux, struct clk *pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct clk *step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define IMX_COMPOSITE_CORE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define IMX_COMPOSITE_BUS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define IMX_COMPOSITE_FW_MANAGED BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) const char * const *parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) int num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) void __iomem *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u32 composite_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define imx8m_clk_hw_composite_bus(name, parent_names, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) imx8m_clk_hw_composite_flags(name, parent_names, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ARRAY_SIZE(parent_names), reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) IMX_COMPOSITE_BUS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define imx8m_clk_hw_composite_bus_critical(name, parent_names, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) imx8m_clk_hw_composite_flags(name, parent_names, ARRAY_SIZE(parent_names), reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) IMX_COMPOSITE_BUS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE | CLK_IS_CRITICAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define imx8m_clk_hw_composite_core(name, parent_names, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) imx8m_clk_hw_composite_flags(name, parent_names, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ARRAY_SIZE(parent_names), reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) IMX_COMPOSITE_CORE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define imx8m_clk_composite_flags(name, parent_names, num_parents, reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) to_clk(imx8m_clk_hw_composite_flags(name, parent_names, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) num_parents, reg, 0, flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define __imx8m_clk_hw_composite(name, parent_names, reg, flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) imx8m_clk_hw_composite_flags(name, parent_names, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ARRAY_SIZE(parent_names), reg, 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define __imx8m_clk_hw_fw_managed_composite(name, parent_names, reg, flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) imx8m_clk_hw_composite_flags(name, parent_names, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ARRAY_SIZE(parent_names), reg, IMX_COMPOSITE_FW_MANAGED, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) flags | CLK_GET_RATE_NOCACHE | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define imx8m_clk_hw_fw_managed_composite(name, parent_names, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) __imx8m_clk_hw_fw_managed_composite(name, parent_names, reg, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define imx8m_clk_hw_fw_managed_composite_critical(name, parent_names, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) __imx8m_clk_hw_fw_managed_composite(name, parent_names, reg, CLK_IS_CRITICAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define __imx8m_clk_composite(name, parent_names, reg, flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) to_clk(__imx8m_clk_hw_composite(name, parent_names, reg, flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define imx8m_clk_hw_composite(name, parent_names, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) __imx8m_clk_hw_composite(name, parent_names, reg, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define imx8m_clk_composite(name, parent_names, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) __imx8m_clk_composite(name, parent_names, reg, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define imx8m_clk_hw_composite_critical(name, parent_names, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) __imx8m_clk_hw_composite(name, parent_names, reg, CLK_IS_CRITICAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define imx8m_clk_composite_critical(name, parent_names, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) __imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) unsigned long flags, void __iomem *reg, u8 shift, u8 width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) u8 clk_divider_flags, const struct clk_div_table *table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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