^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2018 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Dong Aisheng <aisheng.dong@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <dt-bindings/firmware/imx/rsrc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/arm-smccc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "clk-scu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IMX_SIP_CPUFREQ 0xC2000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IMX_SIP_SET_CPUFREQ 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static struct imx_sc_ipc *ccm_ipc_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * struct clk_scu - Description of one SCU clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * @hw: the common clk_hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * @rsrc_id: resource ID of this SCU clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * @clk_type: type of this clock resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct clk_scu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u16 rsrc_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u8 clk_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * struct imx_sc_msg_req_set_clock_rate - clock set rate protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @hdr: SCU protocol header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * @rate: rate to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * @resource: clock resource to set rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * @clk: clk type of this resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * This structure describes the SCU protocol of clock rate set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct imx_sc_msg_req_set_clock_rate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct imx_sc_rpc_msg hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) __le32 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) __le16 resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u8 clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) } __packed __aligned(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct req_get_clock_rate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) __le16 resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u8 clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) } __packed __aligned(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct resp_get_clock_rate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) __le32 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * struct imx_sc_msg_get_clock_rate - clock get rate protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @hdr: SCU protocol header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @req: get rate request protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @resp: get rate response protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * This structure describes the SCU protocol of clock rate get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct imx_sc_msg_get_clock_rate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct imx_sc_rpc_msg hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct req_get_clock_rate req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct resp_get_clock_rate resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) } data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * struct imx_sc_msg_get_clock_parent - clock get parent protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @hdr: SCU protocol header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @req: get parent request protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @resp: get parent response protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * This structure describes the SCU protocol of clock get parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct imx_sc_msg_get_clock_parent {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct imx_sc_rpc_msg hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct req_get_clock_parent {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) __le16 resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u8 clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) } __packed __aligned(4) req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct resp_get_clock_parent {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) } resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) } data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * struct imx_sc_msg_set_clock_parent - clock set parent protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @hdr: SCU protocol header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @req: set parent request protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * This structure describes the SCU protocol of clock set parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct imx_sc_msg_set_clock_parent {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct imx_sc_rpc_msg hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) __le16 resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u8 clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * struct imx_sc_msg_req_clock_enable - clock gate protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @hdr: SCU protocol header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * @resource: clock resource to gate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @clk: clk type of this resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @enable: whether gate off the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @autog: HW auto gate enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * This structure describes the SCU protocol of clock gate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct imx_sc_msg_req_clock_enable {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct imx_sc_rpc_msg hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) __le16 resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u8 clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u8 enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u8 autog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) } __packed __aligned(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static inline struct clk_scu *to_clk_scu(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return container_of(hw, struct clk_scu, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int imx_clk_scu_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return imx_scu_get_handle(&ccm_ipc_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * clk_scu_recalc_rate - Get clock rate for a SCU clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * @hw: clock to get rate for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @parent_rate: parent rate provided by common clock framework, not used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * Gets the current clock rate of a SCU clock. Returns the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * clock rate, or zero in failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static unsigned long clk_scu_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct clk_scu *clk = to_clk_scu(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct imx_sc_msg_get_clock_rate msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct imx_sc_rpc_msg *hdr = &msg.hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) hdr->ver = IMX_SC_RPC_VERSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) hdr->svc = IMX_SC_RPC_SVC_PM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) hdr->func = IMX_SC_PM_FUNC_GET_CLOCK_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) hdr->size = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) msg.data.req.resource = cpu_to_le16(clk->rsrc_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) msg.data.req.clk = clk->clk_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ret = imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) pr_err("%s: failed to get clock rate %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) clk_hw_get_name(hw), ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return le32_to_cpu(msg.data.resp.rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * clk_scu_round_rate - Round clock rate for a SCU clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * @hw: clock to round rate for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * @rate: rate to round
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @parent_rate: parent rate provided by common clock framework, not used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * Returns the current clock rate, or zero in failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static long clk_scu_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Assume we support all the requested rate and let the SCU firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * to handle the left work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int clk_scu_atf_set_cpu_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct clk_scu *clk = to_clk_scu(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned long cluster_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (clk->rsrc_id == IMX_SC_R_A35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) cluster_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* CPU frequency scaling can ONLY be done by ARM-Trusted-Firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) arm_smccc_smc(IMX_SIP_CPUFREQ, IMX_SIP_SET_CPUFREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) cluster_id, rate, 0, 0, 0, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * clk_scu_set_rate - Set rate for a SCU clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * @hw: clock to change rate for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * @rate: target rate for the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * @parent_rate: rate of the clock parent, not used for SCU clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * Sets a clock frequency for a SCU clock. Returns the SCU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * protocol status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int clk_scu_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct clk_scu *clk = to_clk_scu(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct imx_sc_msg_req_set_clock_rate msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct imx_sc_rpc_msg *hdr = &msg.hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) hdr->ver = IMX_SC_RPC_VERSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) hdr->svc = IMX_SC_RPC_SVC_PM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) hdr->func = IMX_SC_PM_FUNC_SET_CLOCK_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) hdr->size = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) msg.rate = cpu_to_le32(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) msg.resource = cpu_to_le16(clk->rsrc_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) msg.clk = clk->clk_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static u8 clk_scu_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct clk_scu *clk = to_clk_scu(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct imx_sc_msg_get_clock_parent msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct imx_sc_rpc_msg *hdr = &msg.hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) hdr->ver = IMX_SC_RPC_VERSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) hdr->svc = IMX_SC_RPC_SVC_PM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) hdr->func = IMX_SC_PM_FUNC_GET_CLOCK_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) hdr->size = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) msg.data.req.resource = cpu_to_le16(clk->rsrc_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) msg.data.req.clk = clk->clk_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ret = imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) pr_err("%s: failed to get clock parent %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) clk_hw_get_name(hw), ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return msg.data.resp.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int clk_scu_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct clk_scu *clk = to_clk_scu(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct imx_sc_msg_set_clock_parent msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct imx_sc_rpc_msg *hdr = &msg.hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) hdr->ver = IMX_SC_RPC_VERSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) hdr->svc = IMX_SC_RPC_SVC_PM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) hdr->func = IMX_SC_PM_FUNC_SET_CLOCK_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) hdr->size = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) msg.resource = cpu_to_le16(clk->rsrc_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) msg.clk = clk->clk_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) msg.parent = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int sc_pm_clock_enable(struct imx_sc_ipc *ipc, u16 resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u8 clk, bool enable, bool autog)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct imx_sc_msg_req_clock_enable msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct imx_sc_rpc_msg *hdr = &msg.hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) hdr->ver = IMX_SC_RPC_VERSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) hdr->svc = IMX_SC_RPC_SVC_PM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) hdr->func = IMX_SC_PM_FUNC_CLOCK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) hdr->size = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) msg.resource = cpu_to_le16(resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) msg.clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) msg.enable = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) msg.autog = autog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * clk_scu_prepare - Enable a SCU clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * @hw: clock to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * Enable the clock at the DSC slice level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int clk_scu_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct clk_scu *clk = to_clk_scu(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return sc_pm_clock_enable(ccm_ipc_handle, clk->rsrc_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) clk->clk_type, true, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * clk_scu_unprepare - Disable a SCU clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * @hw: clock to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * Disable the clock at the DSC slice level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static void clk_scu_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct clk_scu *clk = to_clk_scu(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ret = sc_pm_clock_enable(ccm_ipc_handle, clk->rsrc_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) clk->clk_type, false, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) pr_warn("%s: clk unprepare failed %d\n", clk_hw_get_name(hw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static const struct clk_ops clk_scu_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .recalc_rate = clk_scu_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .round_rate = clk_scu_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .set_rate = clk_scu_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .get_parent = clk_scu_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .set_parent = clk_scu_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .prepare = clk_scu_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .unprepare = clk_scu_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static const struct clk_ops clk_scu_cpu_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .recalc_rate = clk_scu_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .round_rate = clk_scu_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .set_rate = clk_scu_atf_set_cpu_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .prepare = clk_scu_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .unprepare = clk_scu_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct clk_hw *__imx_clk_scu(const char *name, const char * const *parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int num_parents, u32 rsrc_id, u8 clk_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct clk_scu *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) clk = kzalloc(sizeof(*clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (!clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) clk->rsrc_id = rsrc_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) clk->clk_type = clk_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) init.ops = &clk_scu_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (rsrc_id == IMX_SC_R_A35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) init.ops = &clk_scu_cpu_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) init.ops = &clk_scu_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) init.parent_names = parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) init.num_parents = num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * Note on MX8, the clocks are tightly coupled with power domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * that once the power domain is off, the clock status may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * lost. So we make it NOCACHE to let user to retrieve the real
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * clock status from HW instead of using the possible invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * cached rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) init.flags = CLK_GET_RATE_NOCACHE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) clk->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) hw = &clk->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ret = clk_hw_register(NULL, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) kfree(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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