^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2012 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2012 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PLL_NUM_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PLL_DENOM_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PLL_IMX7_NUM_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PLL_IMX7_DENOM_OFFSET 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PLL_VF610_NUM_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PLL_VF610_DENOM_OFFSET 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BM_PLL_POWER (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define BM_PLL_LOCK (0x1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IMX7_ENET_PLL_POWER (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IMX7_DDR_PLL_POWER (0x1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PLL_LOCK_TIMEOUT 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * struct clk_pllv3 - IMX PLL clock version 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @hw: clock source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @base: base address of PLL registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * @power_bit: pll power bit mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * @powerup_set: set power_bit to power up the PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * @div_mask: mask of divider bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * @div_shift: shift of divider bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * @ref_clock: reference clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * @num_offset: num register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @denom_offset: denom register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * is actually a multiplier, and always sits at bit 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct clk_pllv3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 power_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) bool powerup_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 div_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 div_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned long ref_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 num_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 denom_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 val = readl_relaxed(pll->base) & pll->power_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* No need to wait for lock when pll is not powered up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return readl_relaxed_poll_timeout(pll->base, val, val & BM_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 500, PLL_LOCK_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int clk_pllv3_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct clk_pllv3 *pll = to_clk_pllv3(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) val = readl_relaxed(pll->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (pll->powerup_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) val |= pll->power_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) val &= ~pll->power_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) writel_relaxed(val, pll->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return clk_pllv3_wait_lock(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static void clk_pllv3_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct clk_pllv3 *pll = to_clk_pllv3(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) val = readl_relaxed(pll->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (pll->powerup_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) val &= ~pll->power_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) val |= pll->power_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) writel_relaxed(val, pll->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int clk_pllv3_is_prepared(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct clk_pllv3 *pll = to_clk_pllv3(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (readl_relaxed(pll->base) & BM_PLL_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct clk_pllv3 *pll = to_clk_pllv3(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return (div == 1) ? parent_rate * 22 : parent_rate * 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned long parent_rate = *prate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return (rate >= parent_rate * 22) ? parent_rate * 22 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) parent_rate * 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct clk_pllv3 *pll = to_clk_pllv3(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 val, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (rate == parent_rate * 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) else if (rate == parent_rate * 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) div = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) val = readl_relaxed(pll->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) val &= ~(pll->div_mask << pll->div_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) val |= (div << pll->div_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) writel_relaxed(val, pll->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return clk_pllv3_wait_lock(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const struct clk_ops clk_pllv3_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .prepare = clk_pllv3_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .unprepare = clk_pllv3_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .is_prepared = clk_pllv3_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .recalc_rate = clk_pllv3_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .round_rate = clk_pllv3_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .set_rate = clk_pllv3_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct clk_pllv3 *pll = to_clk_pllv3(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 div = readl_relaxed(pll->base) & pll->div_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return parent_rate * div / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned long parent_rate = *prate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned long min_rate = parent_rate * 54 / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned long max_rate = parent_rate * 108 / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (rate > max_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) rate = max_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) else if (rate < min_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) rate = min_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) div = rate * 2 / parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return parent_rate * div / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct clk_pllv3 *pll = to_clk_pllv3(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned long min_rate = parent_rate * 54 / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned long max_rate = parent_rate * 108 / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 val, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (rate < min_rate || rate > max_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) div = rate * 2 / parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) val = readl_relaxed(pll->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) val &= ~pll->div_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) val |= div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) writel_relaxed(val, pll->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return clk_pllv3_wait_lock(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const struct clk_ops clk_pllv3_sys_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .prepare = clk_pllv3_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .unprepare = clk_pllv3_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .is_prepared = clk_pllv3_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .recalc_rate = clk_pllv3_sys_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .round_rate = clk_pllv3_sys_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .set_rate = clk_pllv3_sys_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct clk_pllv3 *pll = to_clk_pllv3(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 mfn = readl_relaxed(pll->base + pll->num_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u32 mfd = readl_relaxed(pll->base + pll->denom_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 div = readl_relaxed(pll->base) & pll->div_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u64 temp64 = (u64)parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) temp64 *= mfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) do_div(temp64, mfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return parent_rate * div + (unsigned long)temp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned long parent_rate = *prate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned long min_rate = parent_rate * 27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) unsigned long max_rate = parent_rate * 54;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 mfn, mfd = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 max_mfd = 0x3FFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u64 temp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (rate > max_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) rate = max_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) else if (rate < min_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) rate = min_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (parent_rate <= max_mfd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) mfd = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) div = rate / parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) temp64 = (u64) (rate - div * parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) temp64 *= mfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) do_div(temp64, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) mfn = temp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) temp64 = (u64)parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) temp64 *= mfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) do_div(temp64, mfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return parent_rate * div + (unsigned long)temp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct clk_pllv3 *pll = to_clk_pllv3(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned long min_rate = parent_rate * 27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned long max_rate = parent_rate * 54;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 val, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 mfn, mfd = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 max_mfd = 0x3FFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u64 temp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (rate < min_rate || rate > max_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (parent_rate <= max_mfd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) mfd = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) div = rate / parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) temp64 = (u64) (rate - div * parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) temp64 *= mfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) do_div(temp64, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) mfn = temp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) val = readl_relaxed(pll->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) val &= ~pll->div_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) val |= div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) writel_relaxed(val, pll->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) writel_relaxed(mfn, pll->base + pll->num_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) writel_relaxed(mfd, pll->base + pll->denom_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return clk_pllv3_wait_lock(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static const struct clk_ops clk_pllv3_av_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .prepare = clk_pllv3_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .unprepare = clk_pllv3_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .is_prepared = clk_pllv3_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .recalc_rate = clk_pllv3_av_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .round_rate = clk_pllv3_av_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .set_rate = clk_pllv3_av_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct clk_pllv3_vf610_mf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 mfi; /* integer part, can be 20 or 22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u32 mfn; /* numerator, 30-bit value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 mfd; /* denominator, 30-bit value, must be less than mfn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static unsigned long clk_pllv3_vf610_mf_to_rate(unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct clk_pllv3_vf610_mf mf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u64 temp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) temp64 = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) temp64 *= mf.mfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) do_div(temp64, mf.mfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return (parent_rate * mf.mfi) + temp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static struct clk_pllv3_vf610_mf clk_pllv3_vf610_rate_to_mf(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned long parent_rate, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct clk_pllv3_vf610_mf mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u64 temp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) mf.mfi = (rate >= 22 * parent_rate) ? 22 : 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) mf.mfd = 0x3fffffff; /* use max supported value for best accuracy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (rate <= parent_rate * mf.mfi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) mf.mfn = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) else if (rate >= parent_rate * (mf.mfi + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) mf.mfn = mf.mfd - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* rate = parent_rate * (mfi + mfn/mfd) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) temp64 = rate - parent_rate * mf.mfi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) temp64 *= mf.mfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) do_div(temp64, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) mf.mfn = temp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static unsigned long clk_pllv3_vf610_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct clk_pllv3 *pll = to_clk_pllv3(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct clk_pllv3_vf610_mf mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) mf.mfn = readl_relaxed(pll->base + pll->num_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) mf.mfd = readl_relaxed(pll->base + pll->denom_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return clk_pllv3_vf610_mf_to_rate(parent_rate, mf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static long clk_pllv3_vf610_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct clk_pllv3_vf610_mf mf = clk_pllv3_vf610_rate_to_mf(*prate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return clk_pllv3_vf610_mf_to_rate(*prate, mf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static int clk_pllv3_vf610_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct clk_pllv3 *pll = to_clk_pllv3(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct clk_pllv3_vf610_mf mf =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) clk_pllv3_vf610_rate_to_mf(parent_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) val = readl_relaxed(pll->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (mf.mfi == 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) val &= ~pll->div_mask; /* clear bit for mfi=20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) val |= pll->div_mask; /* set bit for mfi=22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) writel_relaxed(val, pll->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) writel_relaxed(mf.mfn, pll->base + pll->num_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) writel_relaxed(mf.mfd, pll->base + pll->denom_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return clk_pllv3_wait_lock(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static const struct clk_ops clk_pllv3_vf610_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .prepare = clk_pllv3_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .unprepare = clk_pllv3_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .is_prepared = clk_pllv3_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .recalc_rate = clk_pllv3_vf610_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .round_rate = clk_pllv3_vf610_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .set_rate = clk_pllv3_vf610_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct clk_pllv3 *pll = to_clk_pllv3(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return pll->ref_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static const struct clk_ops clk_pllv3_enet_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .prepare = clk_pllv3_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .unprepare = clk_pllv3_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .is_prepared = clk_pllv3_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .recalc_rate = clk_pllv3_enet_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) const char *parent_name, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u32 div_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct clk_pllv3 *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) const struct clk_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) pll = kzalloc(sizeof(*pll), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (!pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) pll->power_bit = BM_PLL_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) pll->num_offset = PLL_NUM_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) pll->denom_offset = PLL_DENOM_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) case IMX_PLLV3_SYS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ops = &clk_pllv3_sys_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) case IMX_PLLV3_SYS_VF610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ops = &clk_pllv3_vf610_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) pll->num_offset = PLL_VF610_NUM_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) pll->denom_offset = PLL_VF610_DENOM_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) case IMX_PLLV3_USB_VF610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) pll->div_shift = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) case IMX_PLLV3_USB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ops = &clk_pllv3_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) pll->powerup_set = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) case IMX_PLLV3_AV_IMX7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) pll->num_offset = PLL_IMX7_NUM_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) pll->denom_offset = PLL_IMX7_DENOM_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) case IMX_PLLV3_AV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ops = &clk_pllv3_av_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) case IMX_PLLV3_ENET_IMX7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) pll->power_bit = IMX7_ENET_PLL_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) pll->ref_clock = 1000000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ops = &clk_pllv3_enet_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) case IMX_PLLV3_ENET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) pll->ref_clock = 500000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ops = &clk_pllv3_enet_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) case IMX_PLLV3_DDR_IMX7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) pll->power_bit = IMX7_DDR_PLL_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) pll->num_offset = PLL_IMX7_NUM_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) pll->denom_offset = PLL_IMX7_DENOM_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ops = &clk_pllv3_av_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ops = &clk_pllv3_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) pll->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) pll->div_mask = div_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) init.ops = ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) pll->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) hw = &pll->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ret = clk_hw_register(NULL, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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