^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define to_clk_pllv2(clk) (container_of(clk, struct clk_pllv2, clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* PLL Register Offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MXC_PLL_DP_CTL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MXC_PLL_DP_CONFIG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MXC_PLL_DP_OP 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MXC_PLL_DP_MFD 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MXC_PLL_DP_MFN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MXC_PLL_DP_MFNMINUS 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MXC_PLL_DP_MFNPLUS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MXC_PLL_DP_HFS_OP 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MXC_PLL_DP_HFS_MFD 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MXC_PLL_DP_HFS_MFN 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MXC_PLL_DP_MFN_TOGC 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MXC_PLL_DP_DESTAT 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* PLL Register Bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MXC_PLL_DP_CTL_ADE 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MXC_PLL_DP_CTL_HFSM 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MXC_PLL_DP_CTL_PRE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MXC_PLL_DP_CTL_UPEN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MXC_PLL_DP_CTL_RST 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MXC_PLL_DP_CTL_RCP 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MXC_PLL_DP_CTL_PLM 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MXC_PLL_DP_CTL_BRM0 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MXC_PLL_DP_CTL_LRF 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MXC_PLL_DP_CONFIG_BIST 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MXC_PLL_DP_CONFIG_SJC_CE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MXC_PLL_DP_CONFIG_AREN 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MXC_PLL_DP_CONFIG_LDREQ 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MXC_PLL_DP_OP_MFI_OFFSET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MXC_PLL_DP_OP_PDF_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MXC_PLL_DP_OP_PDF_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MXC_PLL_DP_MFD_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MXC_PLL_DP_MFN_OFFSET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct clk_pllv2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static unsigned long __clk_pllv2_recalc_rate(unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 dp_ctl, u32 dp_op, u32 dp_mfd, u32 dp_mfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) long mfi, mfn, mfd, pdf, ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned long dbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u64 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) mfi = (mfi <= 5) ? 5 : mfi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) mfn = dp_mfn & MXC_PLL_DP_MFN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) mfn = sign_extend32(mfn, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ref_clk = 2 * parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (dbl != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ref_clk *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ref_clk /= (pdf + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) temp = (u64) ref_clk * abs(mfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) do_div(temp, mfd + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (mfn < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) temp = (ref_clk * mfi) - temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) temp = (ref_clk * mfi) + temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static unsigned long clk_pllv2_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 dp_op, dp_mfd, dp_mfn, dp_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) void __iomem *pllbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct clk_pllv2 *pll = to_clk_pllv2(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) pllbase = pll->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return __clk_pllv2_recalc_rate(parent_rate, dp_ctl, dp_op, dp_mfd, dp_mfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int __clk_pllv2_set_rate(unsigned long rate, unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 *dp_op, u32 *dp_mfd, u32 *dp_mfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) long mfi, pdf, mfn, mfd = 999999;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u64 temp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned long quad_parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) quad_parent_rate = 4 * parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) pdf = mfi = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) while (++pdf < 16 && mfi < 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) mfi = rate * (pdf+1) / quad_parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (mfi > 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) pdf--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) temp64 = rate * (pdf + 1) - quad_parent_rate * mfi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) do_div(temp64, quad_parent_rate / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) mfn = (long)temp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) reg = mfi << 4 | pdf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) *dp_op = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) *dp_mfd = mfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) *dp_mfn = mfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int clk_pllv2_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct clk_pllv2 *pll = to_clk_pllv2(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) void __iomem *pllbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 dp_ctl, dp_op, dp_mfd, dp_mfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) pllbase = pll->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ret = __clk_pllv2_set_rate(rate, parent_rate, &dp_op, &dp_mfd, &dp_mfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* use dpdck0_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) __raw_writel(dp_op, pllbase + MXC_PLL_DP_OP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) __raw_writel(dp_mfd, pllbase + MXC_PLL_DP_MFD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) __raw_writel(dp_mfn, pllbase + MXC_PLL_DP_MFN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static long clk_pllv2_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 dp_op, dp_mfd, dp_mfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ret = __clk_pllv2_set_rate(rate, *prate, &dp_op, &dp_mfd, &dp_mfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return __clk_pllv2_recalc_rate(*prate, MXC_PLL_DP_CTL_DPDCK0_2_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dp_op, dp_mfd, dp_mfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int clk_pllv2_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct clk_pllv2 *pll = to_clk_pllv2(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) void __iomem *pllbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) pllbase = pll->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Wait for lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (reg & MXC_PLL_DP_CTL_LRF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) } while (++i < MAX_DPLL_WAIT_TRIES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (i == MAX_DPLL_WAIT_TRIES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) pr_err("MX5: pll locking failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static void clk_pllv2_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct clk_pllv2 *pll = to_clk_pllv2(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) void __iomem *pllbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pllbase = pll->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const struct clk_ops clk_pllv2_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .prepare = clk_pllv2_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .unprepare = clk_pllv2_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .recalc_rate = clk_pllv2_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .round_rate = clk_pllv2_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .set_rate = clk_pllv2_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct clk_pllv2 *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) pll = kzalloc(sizeof(*pll), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (!pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) pll->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) init.ops = &clk_pllv2_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) init.parent_names = &parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pll->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) hw = &pll->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ret = clk_hw_register(NULL, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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