^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * pll v1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * @clk_hw clock source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * @parent the parent clock name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * @base base address of pll registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * PLL clock version 1, found on i.MX1/21/25/27/31/35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MFN_BITS (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MFN_SIGN (BIT(MFN_BITS - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MFN_MASK (MFN_SIGN - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct clk_pllv1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) enum imx_pllv1_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static inline bool is_imx1_pllv1(struct clk_pllv1 *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) return pll->type == IMX_PLLV1_IMX1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static inline bool is_imx21_pllv1(struct clk_pllv1 *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return pll->type == IMX_PLLV1_IMX21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static inline bool is_imx27_pllv1(struct clk_pllv1 *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return pll->type == IMX_PLLV1_IMX27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static inline bool mfn_is_negative(struct clk_pllv1 *pll, unsigned int mfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return !is_imx1_pllv1(pll) && !is_imx21_pllv1(pll) && (mfn & MFN_SIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct clk_pllv1 *pll = to_clk_pllv1(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned long long ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int mfn_abs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned int mfi, mfn, mfd, pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) reg = readl(pll->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * Get the resulting clock rate from a PLL register value and the input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * frequency. PLLs with this register layout can be found on i.MX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * i.MX21, i.MX27 and i,MX31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * mfi + mfn / (mfd + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * f = 2 * f_ref * --------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * pd + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) mfi = (reg >> 10) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) mfn = reg & 0x3ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) mfd = (reg >> 16) & 0x3ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) pd = (reg >> 26) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) mfi = mfi <= 5 ? 5 : mfi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) mfn_abs = mfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * 2's complements number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * On i.MX27 the bit 9 is the sign bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (mfn_is_negative(pll, mfn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (is_imx27_pllv1(pll))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) mfn_abs = mfn & MFN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) mfn_abs = BIT(MFN_BITS) - mfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) rate = parent_rate * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) rate /= pd + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ull = (unsigned long long)rate * mfn_abs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) do_div(ull, mfd + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (mfn_is_negative(pll, mfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ull = (rate * mfi) - ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ull = (rate * mfi) + ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const struct clk_ops clk_pllv1_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .recalc_rate = clk_pllv1_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) const char *parent, void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct clk_pllv1 *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) pll = kmalloc(sizeof(*pll), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (!pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) pll->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pll->type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) init.ops = &clk_pllv1_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) init.parent_names = &parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) pll->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) hw = &pll->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ret = clk_hw_register(NULL, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags