^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2017-2018 NXP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define GNRL_CTL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DIV_CTL 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define LOCK_STATUS BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define LOCK_SEL_MASK BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLKE_MASK BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RST_MASK BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BYPASS_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MDIV_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MDIV_MASK GENMASK(21, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PDIV_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PDIV_MASK GENMASK(9, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SDIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SDIV_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define KDIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define KDIV_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LOCK_TIMEOUT_US 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct clk_pll14xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) enum imx_pll14xx_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) const struct imx_pll14xx_rate_table *rate_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int rate_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define to_clk_pll14xx(_hw) container_of(_hw, struct clk_pll14xx, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) PLL_1416X_RATE(1800000000U, 225, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PLL_1416X_RATE(1600000000U, 200, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PLL_1416X_RATE(1500000000U, 375, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PLL_1416X_RATE(1400000000U, 350, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PLL_1416X_RATE(1200000000U, 300, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) PLL_1416X_RATE(1000000000U, 250, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PLL_1416X_RATE(800000000U, 200, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PLL_1416X_RATE(750000000U, 250, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PLL_1416X_RATE(700000000U, 350, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PLL_1416X_RATE(600000000U, 300, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PLL_1443X_RATE(519750000U, 173, 2, 2, 16384),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct imx_pll14xx_clk imx_1443x_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .type = PLL_1443X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .rate_table = imx_pll1443x_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .rate_count = ARRAY_SIZE(imx_pll1443x_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) EXPORT_SYMBOL_GPL(imx_1443x_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct imx_pll14xx_clk imx_1443x_dram_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .type = PLL_1443X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .rate_table = imx_pll1443x_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .rate_count = ARRAY_SIZE(imx_pll1443x_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .flags = CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) EXPORT_SYMBOL_GPL(imx_1443x_dram_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct imx_pll14xx_clk imx_1416x_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .type = PLL_1416X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .rate_table = imx_pll1416x_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .rate_count = ARRAY_SIZE(imx_pll1416x_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) EXPORT_SYMBOL_GPL(imx_1416x_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const struct imx_pll14xx_rate_table *imx_get_pll_settings(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct clk_pll14xx *pll, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) for (i = 0; i < pll->rate_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (rate == rate_table[i].rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return &rate_table[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static long clk_pll14xx_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct clk_pll14xx *pll = to_clk_pll14xx(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Assumming rate_table is in descending order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) for (i = 0; i < pll->rate_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (rate >= rate_table[i].rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return rate_table[i].rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* return minimum supported value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return rate_table[i - 1].rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static unsigned long clk_pll1416x_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct clk_pll14xx *pll = to_clk_pll14xx(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 mdiv, pdiv, sdiv, pll_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u64 fvco = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) pll_div = readl_relaxed(pll->base + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) fvco *= mdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) do_div(fvco, pdiv << sdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return fvco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static unsigned long clk_pll1443x_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct clk_pll14xx *pll = to_clk_pll14xx(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) short int kdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u64 fvco = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) pll_div_ctl0 = readl_relaxed(pll->base + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) pll_div_ctl1 = readl_relaxed(pll->base + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) kdiv = pll_div_ctl1 & KDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* fvco = (m * 65536 + k) * Fin / (p * 65536) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) fvco *= (mdiv * 65536 + kdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) pdiv *= 65536;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) do_div(fvco, pdiv << sdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return fvco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static inline bool clk_pll14xx_mp_change(const struct imx_pll14xx_rate_table *rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 pll_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 old_mdiv, old_pdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) old_pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return readl_poll_timeout(pll->base, val, val & LOCK_STATUS, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) LOCK_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned long prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct clk_pll14xx *pll = to_clk_pll14xx(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) const struct imx_pll14xx_rate_table *rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 tmp, div_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) rate = imx_get_pll_settings(pll, drate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (!rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) drate, clk_hw_get_name(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) tmp = readl_relaxed(pll->base + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (!clk_pll14xx_mp_change(rate, tmp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) tmp |= rate->sdiv << SDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) writel_relaxed(tmp, pll->base + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Bypass clock and set lock to pll output lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) tmp = readl_relaxed(pll->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) tmp |= LOCK_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) writel_relaxed(tmp, pll->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Enable RST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) tmp &= ~RST_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) writel_relaxed(tmp, pll->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Enable BYPASS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) tmp |= BYPASS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) writel(tmp, pll->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) (rate->sdiv << SDIV_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) writel_relaxed(div_val, pll->base + 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * According to SPEC, t3 - t2 need to be greater than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * 1us and 1/FREF, respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * FREF is FIN / Prediv, the prediv is [1, 63], so choose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * 3us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) udelay(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Disable RST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) tmp |= RST_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) writel_relaxed(tmp, pll->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Wait Lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ret = clk_pll14xx_wait_lock(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) tmp &= ~BYPASS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) writel_relaxed(tmp, pll->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned long prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct clk_pll14xx *pll = to_clk_pll14xx(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) const struct imx_pll14xx_rate_table *rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u32 tmp, div_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) rate = imx_get_pll_settings(pll, drate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (!rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) drate, clk_hw_get_name(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) tmp = readl_relaxed(pll->base + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (!clk_pll14xx_mp_change(rate, tmp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) tmp |= rate->sdiv << SDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) writel_relaxed(tmp, pll->base + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) tmp = rate->kdiv << KDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) writel_relaxed(tmp, pll->base + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Enable RST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) tmp = readl_relaxed(pll->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) tmp &= ~RST_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) writel_relaxed(tmp, pll->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Enable BYPASS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) tmp |= BYPASS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) writel_relaxed(tmp, pll->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) (rate->sdiv << SDIV_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) writel_relaxed(div_val, pll->base + 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) writel_relaxed(rate->kdiv << KDIV_SHIFT, pll->base + 0x8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * According to SPEC, t3 - t2 need to be greater than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * 1us and 1/FREF, respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * FREF is FIN / Prediv, the prediv is [1, 63], so choose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * 3us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) udelay(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Disable RST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) tmp |= RST_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) writel_relaxed(tmp, pll->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* Wait Lock*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ret = clk_pll14xx_wait_lock(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) tmp &= ~BYPASS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) writel_relaxed(tmp, pll->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static int clk_pll14xx_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct clk_pll14xx *pll = to_clk_pll14xx(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * RESETB = 1 from 0, PLL starts its normal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * operation after lock time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) val = readl_relaxed(pll->base + GNRL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (val & RST_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) val |= BYPASS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) writel_relaxed(val, pll->base + GNRL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) val |= RST_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) writel_relaxed(val, pll->base + GNRL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ret = clk_pll14xx_wait_lock(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) val &= ~BYPASS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) writel_relaxed(val, pll->base + GNRL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static int clk_pll14xx_is_prepared(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct clk_pll14xx *pll = to_clk_pll14xx(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) val = readl_relaxed(pll->base + GNRL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return (val & RST_MASK) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static void clk_pll14xx_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct clk_pll14xx *pll = to_clk_pll14xx(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * Set RST to 0, power down mode is enabled and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * every digital block is reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) val = readl_relaxed(pll->base + GNRL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) val &= ~RST_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) writel_relaxed(val, pll->base + GNRL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static const struct clk_ops clk_pll1416x_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .prepare = clk_pll14xx_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .unprepare = clk_pll14xx_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .is_prepared = clk_pll14xx_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .recalc_rate = clk_pll1416x_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .round_rate = clk_pll14xx_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .set_rate = clk_pll1416x_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static const struct clk_ops clk_pll1416x_min_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .recalc_rate = clk_pll1416x_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static const struct clk_ops clk_pll1443x_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .prepare = clk_pll14xx_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .unprepare = clk_pll14xx_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .is_prepared = clk_pll14xx_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .recalc_rate = clk_pll1443x_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .round_rate = clk_pll14xx_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .set_rate = clk_pll1443x_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) const char *parent_name, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) const struct imx_pll14xx_clk *pll_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct clk_pll14xx *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) pll = kzalloc(sizeof(*pll), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (!pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) init.flags = pll_clk->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) switch (pll_clk->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) case PLL_1416X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (!pll_clk->rate_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) init.ops = &clk_pll1416x_min_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) init.ops = &clk_pll1416x_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) case PLL_1443X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) init.ops = &clk_pll1443x_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) pr_err("%s: Unknown pll type for pll clk %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) __func__, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) pll->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) pll->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) pll->type = pll_clk->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) pll->rate_table = pll_clk->rate_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) pll->rate_count = pll_clk->rate_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) val = readl_relaxed(pll->base + GNRL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) val &= ~BYPASS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) writel_relaxed(val, pll->base + GNRL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) hw = &pll->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ret = clk_hw_register(dev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) pr_err("%s: failed to register pll %s %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) __func__, name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) EXPORT_SYMBOL_GPL(imx_dev_clk_hw_pll14xx);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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