^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2018 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Dong Aisheng <aisheng.dong@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk-scu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/clock/imx8-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/firmware/imx/rsrc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static int imx8qxp_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct device_node *ccm_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct clk_hw_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct clk_hw **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ret = imx_clk_scu_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) IMX_SCU_CLK_END), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) clk_data->num = IMX_SCU_CLK_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) clks = clk_data->hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Fixed clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) clks[IMX_CLK_DUMMY] = clk_hw_register_fixed_rate(NULL, "dummy", NULL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) clks[IMX_ADMA_IPG_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "dma_ipg_clk_root", NULL, 0, 120000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) clks[IMX_CONN_AXI_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "conn_axi_clk_root", NULL, 0, 333333333);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) clks[IMX_CONN_AHB_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "conn_ahb_clk_root", NULL, 0, 166666666);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) clks[IMX_CONN_IPG_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "conn_ipg_clk_root", NULL, 0, 83333333);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) clks[IMX_DC_AXI_EXT_CLK] = clk_hw_register_fixed_rate(NULL, "dc_axi_ext_clk_root", NULL, 0, 800000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) clks[IMX_DC_AXI_INT_CLK] = clk_hw_register_fixed_rate(NULL, "dc_axi_int_clk_root", NULL, 0, 400000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) clks[IMX_DC_CFG_CLK] = clk_hw_register_fixed_rate(NULL, "dc_cfg_clk_root", NULL, 0, 100000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) clks[IMX_MIPI_IPG_CLK] = clk_hw_register_fixed_rate(NULL, "mipi_ipg_clk_root", NULL, 0, 120000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) clks[IMX_IMG_AXI_CLK] = clk_hw_register_fixed_rate(NULL, "img_axi_clk_root", NULL, 0, 400000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) clks[IMX_IMG_IPG_CLK] = clk_hw_register_fixed_rate(NULL, "img_ipg_clk_root", NULL, 0, 200000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) clks[IMX_IMG_PXL_CLK] = clk_hw_register_fixed_rate(NULL, "img_pxl_clk_root", NULL, 0, 600000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) clks[IMX_HSIO_AXI_CLK] = clk_hw_register_fixed_rate(NULL, "hsio_axi_clk_root", NULL, 0, 400000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) clks[IMX_HSIO_PER_CLK] = clk_hw_register_fixed_rate(NULL, "hsio_per_clk_root", NULL, 0, 133333333);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) clks[IMX_LSIO_MEM_CLK] = clk_hw_register_fixed_rate(NULL, "lsio_mem_clk_root", NULL, 0, 200000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) clks[IMX_LSIO_BUS_CLK] = clk_hw_register_fixed_rate(NULL, "lsio_bus_clk_root", NULL, 0, 100000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* ARM core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) clks[IMX_A35_CLK] = imx_clk_scu("a35_clk", IMX_SC_R_A35, IMX_SC_PM_CLK_CPU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* LSIO SS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) clks[IMX_LSIO_PWM0_CLK] = imx_clk_scu("pwm0_clk", IMX_SC_R_PWM_0, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) clks[IMX_LSIO_PWM1_CLK] = imx_clk_scu("pwm1_clk", IMX_SC_R_PWM_1, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) clks[IMX_LSIO_PWM2_CLK] = imx_clk_scu("pwm2_clk", IMX_SC_R_PWM_2, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) clks[IMX_LSIO_PWM3_CLK] = imx_clk_scu("pwm3_clk", IMX_SC_R_PWM_3, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) clks[IMX_LSIO_PWM4_CLK] = imx_clk_scu("pwm4_clk", IMX_SC_R_PWM_4, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) clks[IMX_LSIO_PWM5_CLK] = imx_clk_scu("pwm5_clk", IMX_SC_R_PWM_5, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) clks[IMX_LSIO_PWM6_CLK] = imx_clk_scu("pwm6_clk", IMX_SC_R_PWM_6, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) clks[IMX_LSIO_PWM7_CLK] = imx_clk_scu("pwm7_clk", IMX_SC_R_PWM_7, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) clks[IMX_LSIO_GPT0_CLK] = imx_clk_scu("gpt0_clk", IMX_SC_R_GPT_0, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) clks[IMX_LSIO_GPT1_CLK] = imx_clk_scu("gpt1_clk", IMX_SC_R_GPT_1, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) clks[IMX_LSIO_GPT2_CLK] = imx_clk_scu("gpt2_clk", IMX_SC_R_GPT_2, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) clks[IMX_LSIO_GPT3_CLK] = imx_clk_scu("gpt3_clk", IMX_SC_R_GPT_3, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) clks[IMX_LSIO_GPT4_CLK] = imx_clk_scu("gpt4_clk", IMX_SC_R_GPT_4, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) clks[IMX_LSIO_FSPI0_CLK] = imx_clk_scu("fspi0_clk", IMX_SC_R_FSPI_0, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) clks[IMX_LSIO_FSPI1_CLK] = imx_clk_scu("fspi1_clk", IMX_SC_R_FSPI_1, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* ADMA SS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) clks[IMX_ADMA_UART0_CLK] = imx_clk_scu("uart0_clk", IMX_SC_R_UART_0, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) clks[IMX_ADMA_UART1_CLK] = imx_clk_scu("uart1_clk", IMX_SC_R_UART_1, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) clks[IMX_ADMA_UART2_CLK] = imx_clk_scu("uart2_clk", IMX_SC_R_UART_2, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) clks[IMX_ADMA_UART3_CLK] = imx_clk_scu("uart3_clk", IMX_SC_R_UART_3, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) clks[IMX_ADMA_SPI0_CLK] = imx_clk_scu("spi0_clk", IMX_SC_R_SPI_0, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) clks[IMX_ADMA_SPI1_CLK] = imx_clk_scu("spi1_clk", IMX_SC_R_SPI_1, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) clks[IMX_ADMA_SPI2_CLK] = imx_clk_scu("spi2_clk", IMX_SC_R_SPI_2, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) clks[IMX_ADMA_SPI3_CLK] = imx_clk_scu("spi3_clk", IMX_SC_R_SPI_3, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) clks[IMX_ADMA_CAN0_CLK] = imx_clk_scu("can0_clk", IMX_SC_R_CAN_0, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) clks[IMX_ADMA_I2C0_CLK] = imx_clk_scu("i2c0_clk", IMX_SC_R_I2C_0, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) clks[IMX_ADMA_I2C1_CLK] = imx_clk_scu("i2c1_clk", IMX_SC_R_I2C_1, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) clks[IMX_ADMA_I2C2_CLK] = imx_clk_scu("i2c2_clk", IMX_SC_R_I2C_2, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) clks[IMX_ADMA_I2C3_CLK] = imx_clk_scu("i2c3_clk", IMX_SC_R_I2C_3, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) clks[IMX_ADMA_FTM0_CLK] = imx_clk_scu("ftm0_clk", IMX_SC_R_FTM_0, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) clks[IMX_ADMA_FTM1_CLK] = imx_clk_scu("ftm1_clk", IMX_SC_R_FTM_1, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) clks[IMX_ADMA_ADC0_CLK] = imx_clk_scu("adc0_clk", IMX_SC_R_ADC_0, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) clks[IMX_ADMA_PWM_CLK] = imx_clk_scu("pwm_clk", IMX_SC_R_LCD_0_PWM_0, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) clks[IMX_ADMA_LCD_CLK] = imx_clk_scu("lcd_clk", IMX_SC_R_LCD_0, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Connectivity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) clks[IMX_CONN_SDHC0_CLK] = imx_clk_scu("sdhc0_clk", IMX_SC_R_SDHC_0, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) clks[IMX_CONN_SDHC1_CLK] = imx_clk_scu("sdhc1_clk", IMX_SC_R_SDHC_1, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) clks[IMX_CONN_SDHC2_CLK] = imx_clk_scu("sdhc2_clk", IMX_SC_R_SDHC_2, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) clks[IMX_CONN_ENET0_ROOT_CLK] = imx_clk_scu("enet0_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) clks[IMX_CONN_ENET0_BYPASS_CLK] = imx_clk_scu("enet0_bypass_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) clks[IMX_CONN_ENET0_RGMII_CLK] = imx_clk_scu("enet0_rgmii_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) clks[IMX_CONN_ENET1_ROOT_CLK] = imx_clk_scu("enet1_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) clks[IMX_CONN_ENET1_BYPASS_CLK] = imx_clk_scu("enet1_bypass_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) clks[IMX_CONN_ENET1_RGMII_CLK] = imx_clk_scu("enet1_rgmii_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) clks[IMX_CONN_GPMI_BCH_IO_CLK] = imx_clk_scu("gpmi_io_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) clks[IMX_CONN_GPMI_BCH_CLK] = imx_clk_scu("gpmi_bch_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) clks[IMX_CONN_USB2_ACLK] = imx_clk_scu("usb3_aclk_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) clks[IMX_CONN_USB2_BUS_CLK] = imx_clk_scu("usb3_bus_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MST_BUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) clks[IMX_CONN_USB2_LPM_CLK] = imx_clk_scu("usb3_lpm_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Display controller SS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) clks[IMX_DC0_DISP0_CLK] = imx_clk_scu("dc0_disp0_clk", IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) clks[IMX_DC0_DISP1_CLK] = imx_clk_scu("dc0_disp1_clk", IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* MIPI-LVDS SS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) clks[IMX_MIPI0_I2C0_CLK] = imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) clks[IMX_MIPI0_I2C1_CLK] = imx_clk_scu("mipi0_i2c1_clk", IMX_SC_R_MIPI_0_I2C_1, IMX_SC_PM_CLK_MISC2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* MIPI CSI SS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) clks[IMX_CSI0_CORE_CLK] = imx_clk_scu("mipi_csi0_core_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) clks[IMX_CSI0_ESC_CLK] = imx_clk_scu("mipi_csi0_esc_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) clks[IMX_CSI0_I2C0_CLK] = imx_clk_scu("mipi_csi0_i2c0_clk", IMX_SC_R_CSI_0_I2C_0, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) clks[IMX_CSI0_PWM0_CLK] = imx_clk_scu("mipi_csi0_pwm0_clk", IMX_SC_R_CSI_0_PWM_0, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* GPU SS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) clks[IMX_GPU0_CORE_CLK] = imx_clk_scu("gpu_core0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_PER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) clks[IMX_GPU0_SHADER_CLK] = imx_clk_scu("gpu_shader0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) for (i = 0; i < clk_data->num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (IS_ERR(clks[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pr_warn("i.MX clk %u: register failed with %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) i, PTR_ERR(clks[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return of_clk_add_hw_provider(ccm_node, of_clk_hw_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const struct of_device_id imx8qxp_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { .compatible = "fsl,scu-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { .compatible = "fsl,imx8qxp-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static struct platform_driver imx8qxp_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .name = "imx8qxp-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .of_match_table = imx8qxp_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .probe = imx8qxp_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) module_platform_driver(imx8qxp_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MODULE_AUTHOR("Aisheng Dong <aisheng.dong@nxp.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MODULE_DESCRIPTION("NXP i.MX8QXP clock driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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