^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2018 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Dong Aisheng <aisheng.dong@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _IMX8QXP_LPCG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _IMX8QXP_LPCG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /*LSIO SS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define LSIO_PWM_0_LPCG 0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define LSIO_PWM_1_LPCG 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define LSIO_PWM_2_LPCG 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define LSIO_PWM_3_LPCG 0x30000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define LSIO_PWM_4_LPCG 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define LSIO_PWM_5_LPCG 0x50000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define LSIO_PWM_6_LPCG 0x60000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define LSIO_PWM_7_LPCG 0x70000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define LSIO_GPIO_0_LPCG 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define LSIO_GPIO_1_LPCG 0x90000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LSIO_GPIO_2_LPCG 0xa0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LSIO_GPIO_3_LPCG 0xb0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LSIO_GPIO_4_LPCG 0xc0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define LSIO_GPIO_5_LPCG 0xd0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LSIO_GPIO_6_LPCG 0xe0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LSIO_GPIO_7_LPCG 0xf0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LSIO_FSPI_0_LPCG 0x120000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LSIO_FSPI_1_LPCG 0x130000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LSIO_GPT_0_LPCG 0x140000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LSIO_GPT_1_LPCG 0x150000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LSIO_GPT_2_LPCG 0x160000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LSIO_GPT_3_LPCG 0x170000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LSIO_GPT_4_LPCG 0x180000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LSIO_OCRAM_LPCG 0x190000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LSIO_KPP_LPCG 0x1a0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LSIO_ROMCP_LPCG 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Connectivity SS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CONN_USDHC_0_LPCG 0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CONN_USDHC_1_LPCG 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CONN_USDHC_2_LPCG 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CONN_ENET_0_LPCG 0x30000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CONN_ENET_1_LPCG 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CONN_DTCP_LPCG 0x50000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CONN_MLB_LPCG 0x60000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CONN_USB_2_LPCG 0x70000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CONN_USB_3_LPCG 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CONN_NAND_LPCG 0x90000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CONN_EDMA_LPCG 0xa0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* ADMA SS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ADMA_ASRC_0_LPCG 0x400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ADMA_ESAI_0_LPCG 0x410000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ADMA_SPDIF_0_LPCG 0x420000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ADMA_SAI_0_LPCG 0x440000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ADMA_SAI_1_LPCG 0x450000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ADMA_SAI_2_LPCG 0x460000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ADMA_SAI_3_LPCG 0x470000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ADMA_GPT_5_LPCG 0x4b0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ADMA_GPT_6_LPCG 0x4c0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ADMA_GPT_7_LPCG 0x4d0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ADMA_GPT_8_LPCG 0x4e0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ADMA_GPT_9_LPCG 0x4f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ADMA_GPT_10_LPCG 0x500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ADMA_HIFI_LPCG 0x580000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ADMA_OCRAM_LPCG 0x590000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ADMA_EDMA_0_LPCG 0x5f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ADMA_ASRC_1_LPCG 0xc00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ADMA_SAI_4_LPCG 0xc20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ADMA_SAI_5_LPCG 0xc30000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ADMA_AMIX_LPCG 0xc40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ADMA_MQS_LPCG 0xc50000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ADMA_ACM_LPCG 0xc60000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ADMA_REC_CLK0_LPCG 0xd00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ADMA_REC_CLK1_LPCG 0xd10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ADMA_PLL_CLK0_LPCG 0xd20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ADMA_PLL_CLK1_LPCG 0xd30000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ADMA_MCLKOUT0_LPCG 0xd50000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ADMA_MCLKOUT1_LPCG 0xd60000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ADMA_EDMA_1_LPCG 0xdf0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ADMA_LPSPI_0_LPCG 0x1400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ADMA_LPSPI_1_LPCG 0x1410000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ADMA_LPSPI_2_LPCG 0x1420000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ADMA_LPSPI_3_LPCG 0x1430000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ADMA_LPUART_0_LPCG 0x1460000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ADMA_LPUART_1_LPCG 0x1470000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ADMA_LPUART_2_LPCG 0x1480000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ADMA_LPUART_3_LPCG 0x1490000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ADMA_LCD_LPCG 0x1580000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ADMA_PWM_LPCG 0x1590000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ADMA_LPI2C_0_LPCG 0x1c00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ADMA_LPI2C_1_LPCG 0x1c10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ADMA_LPI2C_2_LPCG 0x1c20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ADMA_LPI2C_3_LPCG 0x1c30000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ADMA_ADC_0_LPCG 0x1c80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ADMA_FTM_0_LPCG 0x1ca0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ADMA_FTM_1_LPCG 0x1cb0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define ADMA_FLEXCAN_0_LPCG 0x1cd0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ADMA_FLEXCAN_1_LPCG 0x1ce0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ADMA_FLEXCAN_2_LPCG 0x1cf0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #endif /* _IMX8QXP_LPCG_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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