^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2018 NXP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <dt-bindings/clock/imx8mq-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static u32 share_count_sai1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static u32 share_count_sai2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static u32 share_count_sai3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static u32 share_count_sai4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static u32 share_count_sai5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static u32 share_count_sai6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static u32 share_count_dcss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static u32 share_count_nand;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "dummy", "dummy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static const char * const sys3_pll_out_sels[] = {"sys3_pll1_ref_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static const char * const dram_pll_out_sels[] = {"dram_pll1_ref_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static const char * const video2_pll_out_sels[] = {"video2_pll1_ref_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* CCM ROOT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static const char * const imx8mq_a53_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) "sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "sys3_pll_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static const char * const imx8mq_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static const char * const imx8mq_arm_m4_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_250m", "sys1_pll_266m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) "sys1_pll_800m", "audio_pll1_out", "video_pll1_out", "sys3_pll_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static const char * const imx8mq_vpu_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) "sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "vpu_pll_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static const char * const imx8mq_gpu_core_sels[] = {"osc_25m", "gpu_pll_out", "sys1_pll_800m", "sys3_pll_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) "sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const char * const imx8mq_gpu_shader_sels[] = {"osc_25m", "gpu_pll_out", "sys1_pll_800m", "sys3_pll_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) "sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static const char * const imx8mq_main_axi_sels[] = {"osc_25m", "sys2_pll_333m", "sys1_pll_800m", "sys2_pll_250m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) "sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "sys1_pll_100m",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static const char * const imx8mq_enet_axi_sels[] = {"osc_25m", "sys1_pll_266m", "sys1_pll_800m", "sys2_pll_250m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "sys2_pll_200m", "audio_pll1_out", "video_pll1_out", "sys3_pll_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static const char * const imx8mq_nand_usdhc_sels[] = {"osc_25m", "sys1_pll_266m", "sys1_pll_800m", "sys2_pll_200m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "sys1_pll_133m", "sys3_pll_out", "sys2_pll_250m", "audio_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static const char * const imx8mq_vpu_bus_sels[] = {"osc_25m", "sys1_pll_800m", "vpu_pll_out", "audio_pll2_out", "sys3_pll_out", "sys2_pll_1000m", "sys2_pll_200m", "sys1_pll_100m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static const char * const imx8mq_disp_axi_sels[] = {"osc_25m", "sys2_pll_125m", "sys1_pll_800m", "sys3_pll_out", "sys1_pll_400m", "audio_pll2_out", "clk_ext1", "clk_ext4", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static const char * const imx8mq_disp_apb_sels[] = {"osc_25m", "sys2_pll_125m", "sys1_pll_800m", "sys3_pll_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) "sys1_pll_40m", "audio_pll2_out", "clk_ext1", "clk_ext3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static const char * const imx8mq_disp_rtrm_sels[] = {"osc_25m", "sys1_pll_800m", "sys2_pll_200m", "sys1_pll_400m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "audio_pll1_out", "video_pll1_out", "clk_ext2", "clk_ext3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static const char * const imx8mq_usb_bus_sels[] = {"osc_25m", "sys2_pll_500m", "sys1_pll_800m", "sys2_pll_100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) "sys2_pll_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static const char * const imx8mq_gpu_axi_sels[] = {"osc_25m", "sys1_pll_800m", "gpu_pll_out", "sys3_pll_out", "sys2_pll_1000m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const char * const imx8mq_gpu_ahb_sels[] = {"osc_25m", "sys1_pll_800m", "gpu_pll_out", "sys3_pll_out", "sys2_pll_1000m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const char * const imx8mq_noc_sels[] = {"osc_25m", "sys1_pll_800m", "sys3_pll_out", "sys2_pll_1000m", "sys2_pll_500m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const char * const imx8mq_noc_apb_sels[] = {"osc_25m", "sys1_pll_400m", "sys3_pll_out", "sys2_pll_333m", "sys2_pll_200m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "sys1_pll_800m", "audio_pll1_out", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static const char * const imx8mq_ahb_sels[] = {"osc_25m", "sys1_pll_133m", "sys1_pll_800m", "sys1_pll_400m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) "sys2_pll_125m", "sys3_pll_out", "audio_pll1_out", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static const char * const imx8mq_audio_ahb_sels[] = {"osc_25m", "sys2_pll_500m", "sys1_pll_800m", "sys2_pll_1000m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) "sys2_pll_166m", "sys3_pll_out", "audio_pll1_out", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static const char * const imx8mq_dsi_ahb_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) "sys2_pll_1000m", "sys3_pll_out", "clk_ext3", "audio_pll2_out"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const char * const imx8mq_dram_alt_sels[] = {"osc_25m", "sys1_pll_800m", "sys1_pll_100m", "sys2_pll_500m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "sys2_pll_250m", "sys1_pll_400m", "audio_pll1_out", "sys1_pll_266m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const char * const imx8mq_dram_apb_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "sys1_pll_800m", "sys3_pll_out", "sys2_pll_250m", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const char * const imx8mq_vpu_g1_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_100m", "sys2_pll_125m", "sys3_pll_out", "audio_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const char * const imx8mq_vpu_g2_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_100m", "sys2_pll_125m", "sys3_pll_out", "audio_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const char * const imx8mq_disp_dtrc_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll_out", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static const char * const imx8mq_disp_dc8000_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll_out", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const char * const imx8mq_pcie1_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) "sys1_pll_800m", "sys2_pll_500m", "sys2_pll_250m", "sys3_pll_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const char * const imx8mq_pcie1_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1", "clk_ext2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "clk_ext3", "clk_ext4", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const char * const imx8mq_pcie1_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_500m", "sys3_pll_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const char * const imx8mq_dc_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll_out", "clk_ext4", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const char * const imx8mq_lcdif_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll_out", "clk_ext4", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const char * const imx8mq_sai1_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext1", "clk_ext2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const char * const imx8mq_sai2_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext2", "clk_ext3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const char * const imx8mq_sai3_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext3", "clk_ext4", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const char * const imx8mq_sai4_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext1", "clk_ext2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const char * const imx8mq_sai5_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext2", "clk_ext3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static const char * const imx8mq_sai6_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext3", "clk_ext4", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const char * const imx8mq_spdif1_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext2", "clk_ext3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const char * const imx8mq_spdif2_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext3", "clk_ext4", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const char * const imx8mq_enet_ref_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_500m", "sys2_pll_100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) "sys1_pll_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const char * const imx8mq_enet_timer_sels[] = {"osc_25m", "sys2_pll_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) "clk_ext3", "clk_ext4", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const char * const imx8mq_enet_phy_sels[] = {"osc_25m", "sys2_pll_50m", "sys2_pll_125m", "sys2_pll_500m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static const char * const imx8mq_nand_sels[] = {"osc_25m", "sys2_pll_500m", "audio_pll1_out", "sys1_pll_400m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "audio_pll2_out", "sys3_pll_out", "sys2_pll_250m", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static const char * const imx8mq_qspi_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "audio_pll2_out", "sys1_pll_266m", "sys3_pll_out", "sys1_pll_100m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const char * const imx8mq_usdhc1_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) "sys3_pll_out", "sys1_pll_266m", "audio_pll2_out", "sys1_pll_100m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static const char * const imx8mq_usdhc2_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) "sys3_pll_out", "sys1_pll_266m", "audio_pll2_out", "sys1_pll_100m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const char * const imx8mq_i2c1_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll_out", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const char * const imx8mq_i2c2_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll_out", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const char * const imx8mq_i2c3_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll_out", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const char * const imx8mq_i2c4_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll_out", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const char * const imx8mq_uart1_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) "sys3_pll_out", "clk_ext2", "clk_ext4", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const char * const imx8mq_uart2_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) "sys3_pll_out", "clk_ext2", "clk_ext3", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const char * const imx8mq_uart3_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "sys3_pll_out", "clk_ext2", "clk_ext4", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const char * const imx8mq_uart4_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) "sys3_pll_out", "clk_ext2", "clk_ext3", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const char * const imx8mq_usb_core_sels[] = {"osc_25m", "sys1_pll_100m", "sys1_pll_40m", "sys2_pll_100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) "sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const char * const imx8mq_usb_phy_sels[] = {"osc_25m", "sys1_pll_100m", "sys1_pll_40m", "sys2_pll_100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) "sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const char * const imx8mq_gic_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys2_pll_100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) "sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const char * const imx8mq_ecspi1_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "sys1_pll_800m", "sys3_pll_out", "sys2_pll_250m", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const char * const imx8mq_ecspi2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "sys1_pll_800m", "sys3_pll_out", "sys2_pll_250m", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const char * const imx8mq_pwm1_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) "sys3_pll_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const char * const imx8mq_pwm2_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "sys3_pll_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const char * const imx8mq_pwm3_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "sys3_pll_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static const char * const imx8mq_pwm4_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) "sys3_pll_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const char * const imx8mq_gpt1_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_400m", "sys1_pll_40m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) "sys1_pll_80m", "audio_pll1_out", "clk_ext1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const char * const imx8mq_wdog_sels[] = {"osc_25m", "sys1_pll_133m", "sys1_pll_160m", "vpu_pll_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "sys2_pll_125m", "sys3_pll_out", "sys1_pll_80m", "sys2_pll_166m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const char * const imx8mq_wrclk_sels[] = {"osc_25m", "sys1_pll_40m", "vpu_pll_out", "sys3_pll_out", "sys2_pll_200m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) "sys1_pll_266m", "sys2_pll_500m", "sys1_pll_100m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const char * const imx8mq_dsi_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) "sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const char * const imx8mq_dsi_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const char * const imx8mq_dsi_dbi_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_100m", "sys1_pll_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) "sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const char * const imx8mq_dsi_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) "sys2_pll_1000m", "sys3_pll_out", "clk_ext3", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const char * const imx8mq_csi1_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) "sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static const char * const imx8mq_csi1_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) "sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static const char * const imx8mq_csi1_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) "sys2_pll_1000m", "sys3_pll_out", "clk_ext3", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static const char * const imx8mq_csi2_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) "sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static const char * const imx8mq_csi2_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) "sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const char * const imx8mq_csi2_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) "sys2_pll_1000m", "sys3_pll_out", "clk_ext3", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const char * const imx8mq_pcie2_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) "sys1_pll_800m", "sys2_pll_500m", "sys2_pll_333m", "sys3_pll_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static const char * const imx8mq_pcie2_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) "clk_ext2", "clk_ext3", "clk_ext4", "sys1_pll_400m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static const char * const imx8mq_pcie2_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_50m", "sys3_pll_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static const char * const imx8mq_ecspi3_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) "sys1_pll_800m", "sys3_pll_out", "sys2_pll_250m", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static const char * const imx8mq_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const char * const imx8mq_clko1_sels[] = {"osc_25m", "sys1_pll_800m", "osc_27m", "sys1_pll_200m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "audio_pll2_out", "sys2_pll_500m", "vpu_pll_out", "sys1_pll_80m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const char * const imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_400m", "sys2_pll_166m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) "sys3_pll_out", "audio_pll1_out", "video_pll1_out", "ckil", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static struct clk_hw_onecell_data *clk_hw_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static struct clk_hw **hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int imx8mq_clocks_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) IMX8MQ_CLK_END), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (WARN_ON(!clk_hw_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) clk_hw_data->num = IMX8MQ_CLK_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) hws = clk_hw_data->hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) hws[IMX8MQ_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) hws[IMX8MQ_CLK_32K] = imx_obtain_fixed_clk_hw(np, "ckil");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) hws[IMX8MQ_CLK_25M] = imx_obtain_fixed_clk_hw(np, "osc_25m");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) hws[IMX8MQ_CLK_27M] = imx_obtain_fixed_clk_hw(np, "osc_27m");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) hws[IMX8MQ_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) hws[IMX8MQ_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) hws[IMX8MQ_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) hws[IMX8MQ_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (WARN_ON(!base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) hws[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) hws[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) hws[IMX8MQ_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x20, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) hws[IMX8MQ_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) hws[IMX8MQ_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x8, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) hws[IMX8MQ_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x10, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) hws[IMX8MQ_SYS3_PLL1_REF_SEL] = imx_clk_hw_mux("sys3_pll1_ref_sel", base + 0x48, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) hws[IMX8MQ_DRAM_PLL1_REF_SEL] = imx_clk_hw_mux("dram_pll1_ref_sel", base + 0x60, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) hws[IMX8MQ_VIDEO2_PLL1_REF_SEL] = imx_clk_hw_mux("video2_pll1_ref_sel", base + 0x54, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) hws[IMX8MQ_ARM_PLL_REF_DIV] = imx_clk_hw_divider("arm_pll_ref_div", "arm_pll_ref_sel", base + 0x28, 5, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) hws[IMX8MQ_GPU_PLL_REF_DIV] = imx_clk_hw_divider("gpu_pll_ref_div", "gpu_pll_ref_sel", base + 0x18, 5, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) hws[IMX8MQ_VPU_PLL_REF_DIV] = imx_clk_hw_divider("vpu_pll_ref_div", "vpu_pll_ref_sel", base + 0x20, 5, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) hws[IMX8MQ_AUDIO_PLL1_REF_DIV] = imx_clk_hw_divider("audio_pll1_ref_div", "audio_pll1_ref_sel", base + 0x0, 5, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) hws[IMX8MQ_AUDIO_PLL2_REF_DIV] = imx_clk_hw_divider("audio_pll2_ref_div", "audio_pll2_ref_sel", base + 0x8, 5, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) hws[IMX8MQ_VIDEO_PLL1_REF_DIV] = imx_clk_hw_divider("video_pll1_ref_div", "video_pll1_ref_sel", base + 0x10, 5, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) hws[IMX8MQ_ARM_PLL] = imx_clk_hw_frac_pll("arm_pll", "arm_pll_ref_div", base + 0x28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) hws[IMX8MQ_GPU_PLL] = imx_clk_hw_frac_pll("gpu_pll", "gpu_pll_ref_div", base + 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) hws[IMX8MQ_VPU_PLL] = imx_clk_hw_frac_pll("vpu_pll", "vpu_pll_ref_div", base + 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) hws[IMX8MQ_AUDIO_PLL1] = imx_clk_hw_frac_pll("audio_pll1", "audio_pll1_ref_div", base + 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) hws[IMX8MQ_AUDIO_PLL2] = imx_clk_hw_frac_pll("audio_pll2", "audio_pll2_ref_div", base + 0x8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) hws[IMX8MQ_VIDEO_PLL1] = imx_clk_hw_frac_pll("video_pll1", "video_pll1_ref_div", base + 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* PLL bypass out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) hws[IMX8MQ_ARM_PLL_BYPASS] = imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x28, 14, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) hws[IMX8MQ_GPU_PLL_BYPASS] = imx_clk_hw_mux("gpu_pll_bypass", base + 0x18, 14, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) hws[IMX8MQ_VPU_PLL_BYPASS] = imx_clk_hw_mux("vpu_pll_bypass", base + 0x20, 14, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) hws[IMX8MQ_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux("audio_pll1_bypass", base + 0x0, 14, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) hws[IMX8MQ_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux("audio_pll2_bypass", base + 0x8, 14, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) hws[IMX8MQ_VIDEO_PLL1_BYPASS] = imx_clk_hw_mux("video_pll1_bypass", base + 0x10, 14, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* PLL OUT GATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) hws[IMX8MQ_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", base + 0x28, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) hws[IMX8MQ_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x18, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) hws[IMX8MQ_VPU_PLL_OUT] = imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x20, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) hws[IMX8MQ_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", base + 0x0, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) hws[IMX8MQ_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x8, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) hws[IMX8MQ_VIDEO_PLL1_OUT] = imx_clk_hw_gate("video_pll1_out", "video_pll1_bypass", base + 0x10, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) hws[IMX8MQ_SYS1_PLL_OUT] = imx_clk_hw_fixed("sys1_pll_out", 800000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) hws[IMX8MQ_SYS2_PLL_OUT] = imx_clk_hw_fixed("sys2_pll_out", 1000000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) hws[IMX8MQ_SYS3_PLL_OUT] = imx_clk_hw_sscg_pll("sys3_pll_out", sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 0, base + 0x48, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) hws[IMX8MQ_DRAM_PLL_OUT] = imx_clk_hw_sscg_pll("dram_pll_out", dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, base + 0x60, CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) hws[IMX8MQ_VIDEO2_PLL_OUT] = imx_clk_hw_sscg_pll("video2_pll_out", video2_pll_out_sels, ARRAY_SIZE(video2_pll_out_sels), 0, 0, 0, base + 0x54, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* SYS PLL1 fixed output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) hws[IMX8MQ_SYS1_PLL_40M] = imx_clk_hw_fixed_factor("sys1_pll_40m", "sys1_pll_out", 1, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) hws[IMX8MQ_SYS1_PLL_80M] = imx_clk_hw_fixed_factor("sys1_pll_80m", "sys1_pll_out", 1, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) hws[IMX8MQ_SYS1_PLL_100M] = imx_clk_hw_fixed_factor("sys1_pll_100m", "sys1_pll_out", 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) hws[IMX8MQ_SYS1_PLL_133M] = imx_clk_hw_fixed_factor("sys1_pll_133m", "sys1_pll_out", 1, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) hws[IMX8MQ_SYS1_PLL_160M] = imx_clk_hw_fixed_factor("sys1_pll_160m", "sys1_pll_out", 1, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) hws[IMX8MQ_SYS1_PLL_200M] = imx_clk_hw_fixed_factor("sys1_pll_200m", "sys1_pll_out", 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) hws[IMX8MQ_SYS1_PLL_266M] = imx_clk_hw_fixed_factor("sys1_pll_266m", "sys1_pll_out", 1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) hws[IMX8MQ_SYS1_PLL_400M] = imx_clk_hw_fixed_factor("sys1_pll_400m", "sys1_pll_out", 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) hws[IMX8MQ_SYS1_PLL_800M] = imx_clk_hw_fixed_factor("sys1_pll_800m", "sys1_pll_out", 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* SYS PLL2 fixed output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) hws[IMX8MQ_SYS2_PLL_50M] = imx_clk_hw_fixed_factor("sys2_pll_50m", "sys2_pll_out", 1, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) hws[IMX8MQ_SYS2_PLL_100M] = imx_clk_hw_fixed_factor("sys2_pll_100m", "sys2_pll_out", 1, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) hws[IMX8MQ_SYS2_PLL_125M] = imx_clk_hw_fixed_factor("sys2_pll_125m", "sys2_pll_out", 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) hws[IMX8MQ_SYS2_PLL_166M] = imx_clk_hw_fixed_factor("sys2_pll_166m", "sys2_pll_out", 1, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) hws[IMX8MQ_SYS2_PLL_200M] = imx_clk_hw_fixed_factor("sys2_pll_200m", "sys2_pll_out", 1, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) hws[IMX8MQ_SYS2_PLL_250M] = imx_clk_hw_fixed_factor("sys2_pll_250m", "sys2_pll_out", 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) hws[IMX8MQ_SYS2_PLL_333M] = imx_clk_hw_fixed_factor("sys2_pll_333m", "sys2_pll_out", 1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) hws[IMX8MQ_SYS2_PLL_500M] = imx_clk_hw_fixed_factor("sys2_pll_500m", "sys2_pll_out", 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) hws[IMX8MQ_SYS2_PLL_1000M] = imx_clk_hw_fixed_factor("sys2_pll_1000m", "sys2_pll_out", 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (WARN_ON(IS_ERR(base)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* CORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) hws[IMX8MQ_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mq_a53_sels, base + 0x8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) hws[IMX8MQ_CLK_A53_CG] = hws[IMX8MQ_CLK_A53_DIV];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) hws[IMX8MQ_CLK_A53_SRC] = hws[IMX8MQ_CLK_A53_DIV];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) hws[IMX8MQ_CLK_M4_CORE] = imx8m_clk_hw_composite_core("arm_m4_core", imx8mq_arm_m4_sels, base + 0x8080);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) hws[IMX8MQ_CLK_VPU_CORE] = imx8m_clk_hw_composite_core("vpu_core", imx8mq_vpu_sels, base + 0x8100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) hws[IMX8MQ_CLK_GPU_CORE] = imx8m_clk_hw_composite_core("gpu_core", imx8mq_gpu_core_sels, base + 0x8180);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) hws[IMX8MQ_CLK_GPU_SHADER] = imx8m_clk_hw_composite("gpu_shader", imx8mq_gpu_shader_sels, base + 0x8200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* For backwards compatibility */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) hws[IMX8MQ_CLK_M4_SRC] = hws[IMX8MQ_CLK_M4_CORE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) hws[IMX8MQ_CLK_M4_CG] = hws[IMX8MQ_CLK_M4_CORE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) hws[IMX8MQ_CLK_M4_DIV] = hws[IMX8MQ_CLK_M4_CORE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) hws[IMX8MQ_CLK_VPU_SRC] = hws[IMX8MQ_CLK_VPU_CORE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) hws[IMX8MQ_CLK_VPU_CG] = hws[IMX8MQ_CLK_VPU_CORE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) hws[IMX8MQ_CLK_VPU_DIV] = hws[IMX8MQ_CLK_VPU_CORE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) hws[IMX8MQ_CLK_GPU_CORE_SRC] = hws[IMX8MQ_CLK_GPU_CORE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) hws[IMX8MQ_CLK_GPU_CORE_CG] = hws[IMX8MQ_CLK_GPU_CORE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) hws[IMX8MQ_CLK_GPU_CORE_DIV] = hws[IMX8MQ_CLK_GPU_CORE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) hws[IMX8MQ_CLK_GPU_SHADER_SRC] = hws[IMX8MQ_CLK_GPU_SHADER];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) hws[IMX8MQ_CLK_GPU_SHADER_CG] = hws[IMX8MQ_CLK_GPU_SHADER];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) hws[IMX8MQ_CLK_GPU_SHADER_DIV] = hws[IMX8MQ_CLK_GPU_SHADER];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* CORE SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) hws[IMX8MQ_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core", base + 0x9880, 24, 1, imx8mq_a53_core_sels, ARRAY_SIZE(imx8mq_a53_core_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* BUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) hws[IMX8MQ_CLK_MAIN_AXI] = imx8m_clk_hw_composite_bus_critical("main_axi", imx8mq_main_axi_sels, base + 0x8800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) hws[IMX8MQ_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi", imx8mq_enet_axi_sels, base + 0x8880);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) hws[IMX8MQ_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_bus("nand_usdhc_bus", imx8mq_nand_usdhc_sels, base + 0x8900);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) hws[IMX8MQ_CLK_VPU_BUS] = imx8m_clk_hw_composite_bus("vpu_bus", imx8mq_vpu_bus_sels, base + 0x8980);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) hws[IMX8MQ_CLK_DISP_AXI] = imx8m_clk_hw_composite_bus("disp_axi", imx8mq_disp_axi_sels, base + 0x8a00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) hws[IMX8MQ_CLK_DISP_APB] = imx8m_clk_hw_composite_bus("disp_apb", imx8mq_disp_apb_sels, base + 0x8a80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) hws[IMX8MQ_CLK_DISP_RTRM] = imx8m_clk_hw_composite_bus("disp_rtrm", imx8mq_disp_rtrm_sels, base + 0x8b00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) hws[IMX8MQ_CLK_USB_BUS] = imx8m_clk_hw_composite_bus("usb_bus", imx8mq_usb_bus_sels, base + 0x8b80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) hws[IMX8MQ_CLK_GPU_AXI] = imx8m_clk_hw_composite_bus("gpu_axi", imx8mq_gpu_axi_sels, base + 0x8c00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) hws[IMX8MQ_CLK_GPU_AHB] = imx8m_clk_hw_composite_bus("gpu_ahb", imx8mq_gpu_ahb_sels, base + 0x8c80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) hws[IMX8MQ_CLK_NOC] = imx8m_clk_hw_composite_bus_critical("noc", imx8mq_noc_sels, base + 0x8d00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) hws[IMX8MQ_CLK_NOC_APB] = imx8m_clk_hw_composite_bus_critical("noc_apb", imx8mq_noc_apb_sels, base + 0x8d80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* AHB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* AHB clock is used by the AHB bus therefore marked as critical */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) hws[IMX8MQ_CLK_AHB] = imx8m_clk_hw_composite_bus_critical("ahb", imx8mq_ahb_sels, base + 0x9000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) hws[IMX8MQ_CLK_AUDIO_AHB] = imx8m_clk_hw_composite_bus("audio_ahb", imx8mq_audio_ahb_sels, base + 0x9100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* IPG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) hws[IMX8MQ_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb", base + 0x9080, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) hws[IMX8MQ_CLK_IPG_AUDIO_ROOT] = imx_clk_hw_divider2("ipg_audio_root", "audio_ahb", base + 0x9180, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * DRAM clocks are manipulated from TF-A outside clock framework.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * The fw_managed helper sets GET_RATE_NOCACHE and clears SET_PARENT_GATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * as div value should always be read from hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) hws[IMX8MQ_CLK_DRAM_CORE] = imx_clk_hw_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mq_dram_core_sels, ARRAY_SIZE(imx8mq_dram_core_sels), CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) hws[IMX8MQ_CLK_DRAM_ALT] = imx8m_clk_hw_fw_managed_composite("dram_alt", imx8mq_dram_alt_sels, base + 0xa000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) hws[IMX8MQ_CLK_DRAM_APB] = imx8m_clk_hw_fw_managed_composite_critical("dram_apb", imx8mq_dram_apb_sels, base + 0xa080);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) hws[IMX8MQ_CLK_VPU_G1] = imx8m_clk_hw_composite("vpu_g1", imx8mq_vpu_g1_sels, base + 0xa100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) hws[IMX8MQ_CLK_VPU_G2] = imx8m_clk_hw_composite("vpu_g2", imx8mq_vpu_g2_sels, base + 0xa180);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) hws[IMX8MQ_CLK_DISP_DTRC] = imx8m_clk_hw_composite("disp_dtrc", imx8mq_disp_dtrc_sels, base + 0xa200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) hws[IMX8MQ_CLK_DISP_DC8000] = imx8m_clk_hw_composite("disp_dc8000", imx8mq_disp_dc8000_sels, base + 0xa280);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) hws[IMX8MQ_CLK_PCIE1_CTRL] = imx8m_clk_hw_composite("pcie1_ctrl", imx8mq_pcie1_ctrl_sels, base + 0xa300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) hws[IMX8MQ_CLK_PCIE1_PHY] = imx8m_clk_hw_composite("pcie1_phy", imx8mq_pcie1_phy_sels, base + 0xa380);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) hws[IMX8MQ_CLK_PCIE1_AUX] = imx8m_clk_hw_composite("pcie1_aux", imx8mq_pcie1_aux_sels, base + 0xa400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) hws[IMX8MQ_CLK_DC_PIXEL] = imx8m_clk_hw_composite("dc_pixel", imx8mq_dc_pixel_sels, base + 0xa480);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) hws[IMX8MQ_CLK_LCDIF_PIXEL] = imx8m_clk_hw_composite("lcdif_pixel", imx8mq_lcdif_pixel_sels, base + 0xa500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) hws[IMX8MQ_CLK_SAI1] = imx8m_clk_hw_composite("sai1", imx8mq_sai1_sels, base + 0xa580);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) hws[IMX8MQ_CLK_SAI2] = imx8m_clk_hw_composite("sai2", imx8mq_sai2_sels, base + 0xa600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) hws[IMX8MQ_CLK_SAI3] = imx8m_clk_hw_composite("sai3", imx8mq_sai3_sels, base + 0xa680);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) hws[IMX8MQ_CLK_SAI4] = imx8m_clk_hw_composite("sai4", imx8mq_sai4_sels, base + 0xa700);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) hws[IMX8MQ_CLK_SAI5] = imx8m_clk_hw_composite("sai5", imx8mq_sai5_sels, base + 0xa780);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) hws[IMX8MQ_CLK_SAI6] = imx8m_clk_hw_composite("sai6", imx8mq_sai6_sels, base + 0xa800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) hws[IMX8MQ_CLK_SPDIF1] = imx8m_clk_hw_composite("spdif1", imx8mq_spdif1_sels, base + 0xa880);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) hws[IMX8MQ_CLK_SPDIF2] = imx8m_clk_hw_composite("spdif2", imx8mq_spdif2_sels, base + 0xa900);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) hws[IMX8MQ_CLK_ENET_REF] = imx8m_clk_hw_composite("enet_ref", imx8mq_enet_ref_sels, base + 0xa980);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) hws[IMX8MQ_CLK_ENET_TIMER] = imx8m_clk_hw_composite("enet_timer", imx8mq_enet_timer_sels, base + 0xaa00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) hws[IMX8MQ_CLK_ENET_PHY_REF] = imx8m_clk_hw_composite("enet_phy", imx8mq_enet_phy_sels, base + 0xaa80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) hws[IMX8MQ_CLK_NAND] = imx8m_clk_hw_composite("nand", imx8mq_nand_sels, base + 0xab00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) hws[IMX8MQ_CLK_QSPI] = imx8m_clk_hw_composite("qspi", imx8mq_qspi_sels, base + 0xab80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) hws[IMX8MQ_CLK_USDHC1] = imx8m_clk_hw_composite("usdhc1", imx8mq_usdhc1_sels, base + 0xac00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) hws[IMX8MQ_CLK_USDHC2] = imx8m_clk_hw_composite("usdhc2", imx8mq_usdhc2_sels, base + 0xac80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) hws[IMX8MQ_CLK_I2C1] = imx8m_clk_hw_composite("i2c1", imx8mq_i2c1_sels, base + 0xad00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) hws[IMX8MQ_CLK_I2C2] = imx8m_clk_hw_composite("i2c2", imx8mq_i2c2_sels, base + 0xad80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) hws[IMX8MQ_CLK_I2C3] = imx8m_clk_hw_composite("i2c3", imx8mq_i2c3_sels, base + 0xae00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) hws[IMX8MQ_CLK_I2C4] = imx8m_clk_hw_composite("i2c4", imx8mq_i2c4_sels, base + 0xae80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) hws[IMX8MQ_CLK_UART1] = imx8m_clk_hw_composite("uart1", imx8mq_uart1_sels, base + 0xaf00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) hws[IMX8MQ_CLK_UART2] = imx8m_clk_hw_composite("uart2", imx8mq_uart2_sels, base + 0xaf80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) hws[IMX8MQ_CLK_UART3] = imx8m_clk_hw_composite("uart3", imx8mq_uart3_sels, base + 0xb000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) hws[IMX8MQ_CLK_UART4] = imx8m_clk_hw_composite("uart4", imx8mq_uart4_sels, base + 0xb080);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) hws[IMX8MQ_CLK_USB_CORE_REF] = imx8m_clk_hw_composite("usb_core_ref", imx8mq_usb_core_sels, base + 0xb100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) hws[IMX8MQ_CLK_USB_PHY_REF] = imx8m_clk_hw_composite("usb_phy_ref", imx8mq_usb_phy_sels, base + 0xb180);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) hws[IMX8MQ_CLK_GIC] = imx8m_clk_hw_composite_critical("gic", imx8mq_gic_sels, base + 0xb200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) hws[IMX8MQ_CLK_ECSPI1] = imx8m_clk_hw_composite("ecspi1", imx8mq_ecspi1_sels, base + 0xb280);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) hws[IMX8MQ_CLK_ECSPI2] = imx8m_clk_hw_composite("ecspi2", imx8mq_ecspi2_sels, base + 0xb300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) hws[IMX8MQ_CLK_PWM1] = imx8m_clk_hw_composite("pwm1", imx8mq_pwm1_sels, base + 0xb380);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) hws[IMX8MQ_CLK_PWM2] = imx8m_clk_hw_composite("pwm2", imx8mq_pwm2_sels, base + 0xb400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) hws[IMX8MQ_CLK_PWM3] = imx8m_clk_hw_composite("pwm3", imx8mq_pwm3_sels, base + 0xb480);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) hws[IMX8MQ_CLK_PWM4] = imx8m_clk_hw_composite("pwm4", imx8mq_pwm4_sels, base + 0xb500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) hws[IMX8MQ_CLK_GPT1] = imx8m_clk_hw_composite("gpt1", imx8mq_gpt1_sels, base + 0xb580);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) hws[IMX8MQ_CLK_WDOG] = imx8m_clk_hw_composite("wdog", imx8mq_wdog_sels, base + 0xb900);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) hws[IMX8MQ_CLK_WRCLK] = imx8m_clk_hw_composite("wrclk", imx8mq_wrclk_sels, base + 0xb980);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) hws[IMX8MQ_CLK_CLKO1] = imx8m_clk_hw_composite("clko1", imx8mq_clko1_sels, base + 0xba00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) hws[IMX8MQ_CLK_CLKO2] = imx8m_clk_hw_composite("clko2", imx8mq_clko2_sels, base + 0xba80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) hws[IMX8MQ_CLK_DSI_CORE] = imx8m_clk_hw_composite("dsi_core", imx8mq_dsi_core_sels, base + 0xbb00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) hws[IMX8MQ_CLK_DSI_PHY_REF] = imx8m_clk_hw_composite("dsi_phy_ref", imx8mq_dsi_phy_sels, base + 0xbb80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) hws[IMX8MQ_CLK_DSI_DBI] = imx8m_clk_hw_composite("dsi_dbi", imx8mq_dsi_dbi_sels, base + 0xbc00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) hws[IMX8MQ_CLK_DSI_ESC] = imx8m_clk_hw_composite("dsi_esc", imx8mq_dsi_esc_sels, base + 0xbc80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) hws[IMX8MQ_CLK_DSI_AHB] = imx8m_clk_hw_composite("dsi_ahb", imx8mq_dsi_ahb_sels, base + 0x9200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) hws[IMX8MQ_CLK_DSI_IPG_DIV] = imx_clk_hw_divider2("dsi_ipg_div", "dsi_ahb", base + 0x9280, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) hws[IMX8MQ_CLK_CSI1_CORE] = imx8m_clk_hw_composite("csi1_core", imx8mq_csi1_core_sels, base + 0xbd00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) hws[IMX8MQ_CLK_CSI1_PHY_REF] = imx8m_clk_hw_composite("csi1_phy_ref", imx8mq_csi1_phy_sels, base + 0xbd80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) hws[IMX8MQ_CLK_CSI1_ESC] = imx8m_clk_hw_composite("csi1_esc", imx8mq_csi1_esc_sels, base + 0xbe00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) hws[IMX8MQ_CLK_CSI2_CORE] = imx8m_clk_hw_composite("csi2_core", imx8mq_csi2_core_sels, base + 0xbe80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) hws[IMX8MQ_CLK_CSI2_PHY_REF] = imx8m_clk_hw_composite("csi2_phy_ref", imx8mq_csi2_phy_sels, base + 0xbf00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) hws[IMX8MQ_CLK_CSI2_ESC] = imx8m_clk_hw_composite("csi2_esc", imx8mq_csi2_esc_sels, base + 0xbf80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) hws[IMX8MQ_CLK_PCIE2_CTRL] = imx8m_clk_hw_composite("pcie2_ctrl", imx8mq_pcie2_ctrl_sels, base + 0xc000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) hws[IMX8MQ_CLK_PCIE2_PHY] = imx8m_clk_hw_composite("pcie2_phy", imx8mq_pcie2_phy_sels, base + 0xc080);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) hws[IMX8MQ_CLK_PCIE2_AUX] = imx8m_clk_hw_composite("pcie2_aux", imx8mq_pcie2_aux_sels, base + 0xc100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) hws[IMX8MQ_CLK_ECSPI3] = imx8m_clk_hw_composite("ecspi3", imx8mq_ecspi3_sels, base + 0xc180);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) hws[IMX8MQ_CLK_ECSPI1_ROOT] = imx_clk_hw_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) hws[IMX8MQ_CLK_ECSPI2_ROOT] = imx_clk_hw_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) hws[IMX8MQ_CLK_ECSPI3_ROOT] = imx_clk_hw_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) hws[IMX8MQ_CLK_ENET1_ROOT] = imx_clk_hw_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) hws[IMX8MQ_CLK_GPIO1_ROOT] = imx_clk_hw_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) hws[IMX8MQ_CLK_GPIO2_ROOT] = imx_clk_hw_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) hws[IMX8MQ_CLK_GPIO3_ROOT] = imx_clk_hw_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) hws[IMX8MQ_CLK_GPIO4_ROOT] = imx_clk_hw_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) hws[IMX8MQ_CLK_GPIO5_ROOT] = imx_clk_hw_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) hws[IMX8MQ_CLK_GPT1_ROOT] = imx_clk_hw_gate4("gpt1_root_clk", "gpt1", base + 0x4100, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) hws[IMX8MQ_CLK_I2C1_ROOT] = imx_clk_hw_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) hws[IMX8MQ_CLK_I2C2_ROOT] = imx_clk_hw_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) hws[IMX8MQ_CLK_I2C3_ROOT] = imx_clk_hw_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) hws[IMX8MQ_CLK_I2C4_ROOT] = imx_clk_hw_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) hws[IMX8MQ_CLK_MU_ROOT] = imx_clk_hw_gate4("mu_root_clk", "ipg_root", base + 0x4210, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) hws[IMX8MQ_CLK_OCOTP_ROOT] = imx_clk_hw_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) hws[IMX8MQ_CLK_PCIE1_ROOT] = imx_clk_hw_gate4("pcie1_root_clk", "pcie1_ctrl", base + 0x4250, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) hws[IMX8MQ_CLK_PCIE2_ROOT] = imx_clk_hw_gate4("pcie2_root_clk", "pcie2_ctrl", base + 0x4640, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) hws[IMX8MQ_CLK_PWM1_ROOT] = imx_clk_hw_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) hws[IMX8MQ_CLK_PWM2_ROOT] = imx_clk_hw_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) hws[IMX8MQ_CLK_PWM3_ROOT] = imx_clk_hw_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) hws[IMX8MQ_CLK_PWM4_ROOT] = imx_clk_hw_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) hws[IMX8MQ_CLK_QSPI_ROOT] = imx_clk_hw_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) hws[IMX8MQ_CLK_RAWNAND_ROOT] = imx_clk_hw_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) hws[IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_hw_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus", base + 0x4300, 0, &share_count_nand);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) hws[IMX8MQ_CLK_SAI1_ROOT] = imx_clk_hw_gate2_shared2("sai1_root_clk", "sai1", base + 0x4330, 0, &share_count_sai1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) hws[IMX8MQ_CLK_SAI1_IPG] = imx_clk_hw_gate2_shared2("sai1_ipg_clk", "ipg_audio_root", base + 0x4330, 0, &share_count_sai1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) hws[IMX8MQ_CLK_SAI2_ROOT] = imx_clk_hw_gate2_shared2("sai2_root_clk", "sai2", base + 0x4340, 0, &share_count_sai2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) hws[IMX8MQ_CLK_SAI2_IPG] = imx_clk_hw_gate2_shared2("sai2_ipg_clk", "ipg_root", base + 0x4340, 0, &share_count_sai2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) hws[IMX8MQ_CLK_SAI3_ROOT] = imx_clk_hw_gate2_shared2("sai3_root_clk", "sai3", base + 0x4350, 0, &share_count_sai3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) hws[IMX8MQ_CLK_SAI3_IPG] = imx_clk_hw_gate2_shared2("sai3_ipg_clk", "ipg_root", base + 0x4350, 0, &share_count_sai3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) hws[IMX8MQ_CLK_SAI4_ROOT] = imx_clk_hw_gate2_shared2("sai4_root_clk", "sai4", base + 0x4360, 0, &share_count_sai4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) hws[IMX8MQ_CLK_SAI4_IPG] = imx_clk_hw_gate2_shared2("sai4_ipg_clk", "ipg_audio_root", base + 0x4360, 0, &share_count_sai4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) hws[IMX8MQ_CLK_SAI5_ROOT] = imx_clk_hw_gate2_shared2("sai5_root_clk", "sai5", base + 0x4370, 0, &share_count_sai5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) hws[IMX8MQ_CLK_SAI5_IPG] = imx_clk_hw_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) hws[IMX8MQ_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) hws[IMX8MQ_CLK_SAI6_IPG] = imx_clk_hw_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) hws[IMX8MQ_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk", "ipg_root", base + 0x4470, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) hws[IMX8MQ_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk", "uart1", base + 0x4490, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) hws[IMX8MQ_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) hws[IMX8MQ_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) hws[IMX8MQ_CLK_UART4_ROOT] = imx_clk_hw_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) hws[IMX8MQ_CLK_USB1_CTRL_ROOT] = imx_clk_hw_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) hws[IMX8MQ_CLK_USB2_CTRL_ROOT] = imx_clk_hw_gate4("usb2_ctrl_root_clk", "usb_bus", base + 0x44e0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) hws[IMX8MQ_CLK_USB1_PHY_ROOT] = imx_clk_hw_gate4("usb1_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) hws[IMX8MQ_CLK_USB2_PHY_ROOT] = imx_clk_hw_gate4("usb2_phy_root_clk", "usb_phy_ref", base + 0x4500, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) hws[IMX8MQ_CLK_USDHC1_ROOT] = imx_clk_hw_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) hws[IMX8MQ_CLK_USDHC2_ROOT] = imx_clk_hw_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) hws[IMX8MQ_CLK_WDOG1_ROOT] = imx_clk_hw_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) hws[IMX8MQ_CLK_WDOG2_ROOT] = imx_clk_hw_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) hws[IMX8MQ_CLK_WDOG3_ROOT] = imx_clk_hw_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) hws[IMX8MQ_CLK_VPU_G1_ROOT] = imx_clk_hw_gate2_flags("vpu_g1_root_clk", "vpu_g1", base + 0x4560, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) hws[IMX8MQ_CLK_GPU_ROOT] = imx_clk_hw_gate4("gpu_root_clk", "gpu_core", base + 0x4570, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) hws[IMX8MQ_CLK_VPU_G2_ROOT] = imx_clk_hw_gate2_flags("vpu_g2_root_clk", "vpu_g2", base + 0x45a0, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) hws[IMX8MQ_CLK_DISP_ROOT] = imx_clk_hw_gate2_shared2("disp_root_clk", "disp_dc8000", base + 0x45d0, 0, &share_count_dcss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) hws[IMX8MQ_CLK_DISP_AXI_ROOT] = imx_clk_hw_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_dcss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) hws[IMX8MQ_CLK_DISP_APB_ROOT] = imx_clk_hw_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_dcss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) hws[IMX8MQ_CLK_DISP_RTRM_ROOT] = imx_clk_hw_gate2_shared2("disp_rtrm_root_clk", "disp_rtrm", base + 0x45d0, 0, &share_count_dcss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) hws[IMX8MQ_CLK_TMU_ROOT] = imx_clk_hw_gate4("tmu_root_clk", "ipg_root", base + 0x4620, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) hws[IMX8MQ_CLK_VPU_DEC_ROOT] = imx_clk_hw_gate2_flags("vpu_dec_root_clk", "vpu_bus", base + 0x4630, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) hws[IMX8MQ_CLK_CSI1_ROOT] = imx_clk_hw_gate4("csi1_root_clk", "csi1_core", base + 0x4650, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) hws[IMX8MQ_CLK_CSI2_ROOT] = imx_clk_hw_gate4("csi2_root_clk", "csi2_core", base + 0x4660, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) hws[IMX8MQ_CLK_SDMA1_ROOT] = imx_clk_hw_gate4("sdma1_clk", "ipg_root", base + 0x43a0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) hws[IMX8MQ_CLK_SDMA2_ROOT] = imx_clk_hw_gate4("sdma2_clk", "ipg_audio_root", base + 0x43b0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) hws[IMX8MQ_GPT_3M_CLK] = imx_clk_hw_fixed_factor("gpt_3m", "osc_25m", 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) hws[IMX8MQ_CLK_DRAM_ALT_ROOT] = imx_clk_hw_fixed_factor("dram_alt_root", "dram_alt", 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) hws[IMX8MQ_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) hws[IMX8MQ_CLK_A53_CORE]->clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) hws[IMX8MQ_CLK_A53_CORE]->clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) hws[IMX8MQ_ARM_PLL_OUT]->clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) hws[IMX8MQ_CLK_A53_DIV]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) imx_check_clk_hws(hws, IMX8MQ_CLK_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) err = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) dev_err(dev, "failed to register hws for i.MX8MQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) goto unregister_hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) imx_register_uart_clocks(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) unregister_hws:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) imx_unregister_hw_clocks(hws, IMX8MQ_CLK_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static const struct of_device_id imx8mq_clk_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) { .compatible = "fsl,imx8mq-ccm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) { /* Sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) MODULE_DEVICE_TABLE(of, imx8mq_clk_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static struct platform_driver imx8mq_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .probe = imx8mq_clocks_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .name = "imx8mq-ccm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * Disable bind attributes: clocks are not removed and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * reloading the driver will crash or break devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .of_match_table = of_match_ptr(imx8mq_clk_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) module_platform_driver(imx8mq_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) MODULE_AUTHOR("Abel Vesa <abel.vesa@nxp.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) MODULE_DESCRIPTION("NXP i.MX8MQ clock driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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