^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2019 NXP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <dt-bindings/clock/imx8mp-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static u32 share_count_nand;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static u32 share_count_media;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static const char * const sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static const char * const imx8mp_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) "audio_pll1_out", "sys_pll3_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static const char * const imx8mp_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static const char * const imx8mp_m7_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) "vpu_pll_out", "sys_pll1_800m", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) "video_pll1_out", "sys_pll3_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static const char * const imx8mp_ml_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "video_pll1_out", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const char * const imx8mp_gpu3d_core_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) "video_pll1_out", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static const char * const imx8mp_gpu3d_shader_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) "video_pll1_out", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const char * const imx8mp_gpu2d_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) "video_pll1_out", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static const char * const imx8mp_audio_axi_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) "video_pll1_out", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static const char * const imx8mp_hsio_axi_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "clk_ext4", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static const char * const imx8mp_media_isp_sels[] = {"osc_24m", "sys_pll2_1000m", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "sys_pll3_out", "sys_pll1_400m", "audio_pll2_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) "clk_ext1", "sys_pll2_500m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static const char * const imx8mp_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) "video_pll1_out", "sys_pll1_100m",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static const char * const imx8mp_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) "video_pll1_out", "sys_pll3_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static const char * const imx8mp_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "sys_pll2_250m", "audio_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const char * const imx8mp_vpu_bus_sels[] = {"osc_24m", "sys_pll1_800m", "vpu_pll_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "audio_pll2_out", "sys_pll3_out", "sys_pll2_1000m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) "sys_pll2_200m", "sys_pll1_100m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static const char * const imx8mp_media_axi_sels[] = {"osc_24m", "sys_pll2_1000m", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "sys_pll3_out", "sys_pll1_40m", "audio_pll2_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "clk_ext1", "sys_pll2_500m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static const char * const imx8mp_media_apb_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "sys_pll3_out", "sys_pll1_40m", "audio_pll2_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) "clk_ext1", "sys_pll1_133m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static const char * const imx8mp_gpu_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) "video_pll1_out", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static const char * const imx8mp_gpu_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) "video_pll1_out", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const char * const imx8mp_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "video_pll1_out", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const char * const imx8mp_noc_io_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "video_pll1_out", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const char * const imx8mp_ml_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) "video_pll1_out", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const char * const imx8mp_ml_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "video_pll1_out", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const char * const imx8mp_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) "audio_pll1_out", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const char * const imx8mp_audio_ahb_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) "sys_pll2_1000m", "sys_pll2_166m", "sys_pll3_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "audio_pll1_out", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const char * const imx8mp_mipi_dsi_esc_rx_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) "sys_pll1_800m", "sys_pll2_1000m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) "sys_pll3_out", "clk_ext3", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const char * const imx8mp_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) "sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) "audio_pll1_out", "sys_pll1_266m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const char * const imx8mp_dram_apb_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) "sys_pll2_250m", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static const char * const imx8mp_vpu_g1_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) "sys_pll2_1000m", "sys_pll1_100m", "sys_pll2_125m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) "sys_pll3_out", "audio_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const char * const imx8mp_vpu_g2_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) "sys_pll2_1000m", "sys_pll1_100m", "sys_pll2_125m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) "sys_pll3_out", "audio_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const char * const imx8mp_can1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) "sys_pll2_250m", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const char * const imx8mp_can2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) "sys_pll2_250m", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const char * const imx8mp_pcie_phy_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll2_500m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "clk_ext1", "clk_ext2", "clk_ext3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "clk_ext4", "sys_pll1_400m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const char * const imx8mp_pcie_aux_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) "sys_pll3_out", "sys_pll2_100m", "sys_pll1_80m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) "sys_pll1_160m", "sys_pll1_200m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const char * const imx8mp_i2c5_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) "audio_pll2_out", "sys_pll1_133m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const char * const imx8mp_i2c6_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) "audio_pll2_out", "sys_pll1_133m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const char * const imx8mp_sai1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "clk_ext1", "clk_ext2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const char * const imx8mp_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) "clk_ext2", "clk_ext3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const char * const imx8mp_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) "clk_ext3", "clk_ext4", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const char * const imx8mp_sai4_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "clk_ext1", "clk_ext2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const char * const imx8mp_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) "clk_ext2", "clk_ext3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const char * const imx8mp_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) "clk_ext3", "clk_ext4", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const char * const imx8mp_enet_qos_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) "video_pll1_out", "clk_ext4", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const char * const imx8mp_enet_qos_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) "clk_ext1", "clk_ext2", "clk_ext3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) "clk_ext4", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const char * const imx8mp_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) "video_pll1_out", "clk_ext4", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const char * const imx8mp_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "clk_ext1", "clk_ext2", "clk_ext3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "clk_ext4", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const char * const imx8mp_enet_phy_ref_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "video_pll1_out", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const char * const imx8mp_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) "sys_pll1_400m", "audio_pll2_out", "sys_pll3_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) "sys_pll2_250m", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const char * const imx8mp_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "sys_pll3_out", "sys_pll1_100m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static const char * const imx8mp_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) "audio_pll2_out", "sys_pll1_100m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const char * const imx8mp_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "audio_pll2_out", "sys_pll1_100m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const char * const imx8mp_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) "audio_pll2_out", "sys_pll1_133m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const char * const imx8mp_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) "audio_pll2_out", "sys_pll1_133m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const char * const imx8mp_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) "audio_pll2_out", "sys_pll1_133m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static const char * const imx8mp_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) "audio_pll2_out", "sys_pll1_133m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const char * const imx8mp_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) "clk_ext4", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const char * const imx8mp_uart2_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) "clk_ext3", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const char * const imx8mp_uart3_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) "clk_ext4", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static const char * const imx8mp_uart4_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) "clk_ext3", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const char * const imx8mp_usb_core_ref_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) "clk_ext3", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static const char * const imx8mp_usb_phy_ref_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "clk_ext3", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static const char * const imx8mp_gic_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) "sys_pll2_100m", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) "sys_pll2_500m", "clk_ext4", "audio_pll2_out" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const char * const imx8mp_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) "sys_pll2_250m", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static const char * const imx8mp_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) "sys_pll2_250m", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static const char * const imx8mp_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) "sys_pll1_40m", "sys_pll3_out", "clk_ext1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) "sys_pll1_80m", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static const char * const imx8mp_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) "sys_pll1_40m", "sys_pll3_out", "clk_ext1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) "sys_pll1_80m", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const char * const imx8mp_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) "sys_pll1_40m", "sys_pll3_out", "clk_ext2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) "sys_pll1_80m", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static const char * const imx8mp_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) "sys_pll1_40m", "sys_pll3_out", "clk_ext2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) "sys_pll1_80m", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const char * const imx8mp_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) "audio_pll1_out", "clk_ext1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static const char * const imx8mp_gpt2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) "audio_pll1_out", "clk_ext2" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const char * const imx8mp_gpt3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) "audio_pll1_out", "clk_ext3" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static const char * const imx8mp_gpt4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) "audio_pll1_out", "clk_ext1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static const char * const imx8mp_gpt5_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) "audio_pll1_out", "clk_ext2" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const char * const imx8mp_gpt6_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) "audio_pll1_out", "clk_ext3" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static const char * const imx8mp_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) "sys_pll1_80m", "sys_pll2_166m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static const char * const imx8mp_wrclk_sels[] = {"osc_24m", "sys_pll1_40m", "vpu_pll_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) "sys_pll3_out", "sys_pll2_200m", "sys_pll1_266m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) "sys_pll2_500m", "sys_pll1_100m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static const char * const imx8mp_ipp_do_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_133m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) "sys_pll1_200m", "audio_pll2_out", "sys_pll2_500m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) "vpu_pll_out", "sys_pll1_80m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const char * const imx8mp_ipp_do_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) "sys_pll1_166m", "sys_pll3_out", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) "video_pll1_out", "osc_32k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static const char * const imx8mp_hdmi_fdcc_tst_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) "audio_pll2_out", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static const char * const imx8mp_hdmi_24m_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) "audio_pll2_out", "sys_pll1_133m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static const char * const imx8mp_hdmi_ref_266m_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll3_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) "sys_pll2_333m", "sys_pll1_266m", "sys_pll2_200m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) "audio_pll1_out", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static const char * const imx8mp_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) "audio_pll2_out", "sys_pll1_100m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const char * const imx8mp_media_cam1_pix_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) "sys_pll1_800m", "sys_pll2_1000m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) "sys_pll3_out", "audio_pll2_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const char * const imx8mp_media_mipi_phy1_ref_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) "sys_pll1_800m", "sys_pll2_1000m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) "clk_ext2", "audio_pll2_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static const char * const imx8mp_media_disp1_pix_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) "audio_pll1_out", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static const char * const imx8mp_media_cam2_pix_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) "sys_pll1_800m", "sys_pll2_1000m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) "sys_pll3_out", "audio_pll2_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static const char * const imx8mp_media_ldb_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) "sys_pll1_800m", "sys_pll2_1000m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) "clk_ext2", "audio_pll2_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const char * const imx8mp_memrepair_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) "clk_ext3", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const char * const imx8mp_pcie2_ctrl_sels[] = {"osc_24m", "sys_pll2_250m", "sys_pll2_200m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_500m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) "sys_pll2_333m", "sys_pll3_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const char * const imx8mp_pcie2_phy_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll2_500m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) "clk_ext1", "clk_ext2", "clk_ext3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) "clk_ext4", "sys_pll1_400m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static const char * const imx8mp_media_mipi_test_byte_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) "sys_pll3_out", "sys_pll2_100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) "sys_pll1_80m", "sys_pll1_160m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) "sys_pll1_200m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static const char * const imx8mp_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) "sys_pll2_250m", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static const char * const imx8mp_pdm_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) "clk_ext3", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const char * const imx8mp_vpu_vc8000e_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) "sys_pll2_1000m", "audio_pll2_out", "sys_pll2_125m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) "sys_pll3_out", "audio_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const char * const imx8mp_sai7_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) "clk_ext3", "clk_ext4", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static const char * const imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static struct clk_hw **hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static struct clk_hw_onecell_data *clk_hw_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static int imx8mp_clocks_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) void __iomem *anatop_base, *ccm_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) np = of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) anatop_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (WARN_ON(!anatop_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ccm_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (WARN_ON(IS_ERR(ccm_base))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) iounmap(anatop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return PTR_ERR(ccm_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, IMX8MP_CLK_END), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (WARN_ON(!clk_hw_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) iounmap(anatop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) clk_hw_data->num = IMX8MP_CLK_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) hws = clk_hw_data->hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) hws[IMX8MP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) hws[IMX8MP_CLK_24M] = imx_obtain_fixed_clk_hw(np, "osc_24m");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) hws[IMX8MP_CLK_32K] = imx_obtain_fixed_clk_hw(np, "osc_32k");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) hws[IMX8MP_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) hws[IMX8MP_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) hws[IMX8MP_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) hws[IMX8MP_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) hws[IMX8MP_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", anatop_base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) hws[IMX8MP_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", anatop_base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) hws[IMX8MP_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", anatop_base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) hws[IMX8MP_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", anatop_base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) hws[IMX8MP_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", anatop_base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) hws[IMX8MP_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", anatop_base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) hws[IMX8MP_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", anatop_base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) hws[IMX8MP_SYS_PLL1_REF_SEL] = imx_clk_hw_mux("sys_pll1_ref_sel", anatop_base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) hws[IMX8MP_SYS_PLL2_REF_SEL] = imx_clk_hw_mux("sys_pll2_ref_sel", anatop_base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) hws[IMX8MP_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", anatop_base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) hws[IMX8MP_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", anatop_base, &imx_1443x_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) hws[IMX8MP_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", anatop_base + 0x14, &imx_1443x_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) hws[IMX8MP_VIDEO_PLL1] = imx_clk_hw_pll14xx("video_pll1", "video_pll1_ref_sel", anatop_base + 0x28, &imx_1443x_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) hws[IMX8MP_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", anatop_base + 0x50, &imx_1443x_dram_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) hws[IMX8MP_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", anatop_base + 0x64, &imx_1416x_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) hws[IMX8MP_VPU_PLL] = imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", anatop_base + 0x74, &imx_1416x_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) hws[IMX8MP_ARM_PLL] = imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", anatop_base + 0x84, &imx_1416x_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) hws[IMX8MP_SYS_PLL1] = imx_clk_hw_pll14xx("sys_pll1", "sys_pll1_ref_sel", anatop_base + 0x94, &imx_1416x_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) hws[IMX8MP_SYS_PLL2] = imx_clk_hw_pll14xx("sys_pll2", "sys_pll2_ref_sel", anatop_base + 0x104, &imx_1416x_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) hws[IMX8MP_SYS_PLL3] = imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", anatop_base + 0x114, &imx_1416x_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) hws[IMX8MP_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", anatop_base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) hws[IMX8MP_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", anatop_base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) hws[IMX8MP_VIDEO_PLL1_BYPASS] = imx_clk_hw_mux_flags("video_pll1_bypass", anatop_base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) hws[IMX8MP_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", anatop_base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) hws[IMX8MP_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", anatop_base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) hws[IMX8MP_VPU_PLL_BYPASS] = imx_clk_hw_mux_flags("vpu_pll_bypass", anatop_base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) hws[IMX8MP_ARM_PLL_BYPASS] = imx_clk_hw_mux_flags("arm_pll_bypass", anatop_base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) hws[IMX8MP_SYS_PLL1_BYPASS] = imx_clk_hw_mux_flags("sys_pll1_bypass", anatop_base + 0x94, 28, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) hws[IMX8MP_SYS_PLL2_BYPASS] = imx_clk_hw_mux_flags("sys_pll2_bypass", anatop_base + 0x104, 28, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) hws[IMX8MP_SYS_PLL3_BYPASS] = imx_clk_hw_mux_flags("sys_pll3_bypass", anatop_base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) hws[IMX8MP_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", anatop_base, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) hws[IMX8MP_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", anatop_base + 0x14, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) hws[IMX8MP_VIDEO_PLL1_OUT] = imx_clk_hw_gate("video_pll1_out", "video_pll1_bypass", anatop_base + 0x28, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) hws[IMX8MP_DRAM_PLL_OUT] = imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", anatop_base + 0x50, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) hws[IMX8MP_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", anatop_base + 0x64, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) hws[IMX8MP_VPU_PLL_OUT] = imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass", anatop_base + 0x74, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) hws[IMX8MP_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", anatop_base + 0x84, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) hws[IMX8MP_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", anatop_base + 0x114, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) hws[IMX8MP_SYS_PLL1_40M_CG] = imx_clk_hw_gate("sys_pll1_40m_cg", "sys_pll1_bypass", anatop_base + 0x94, 27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) hws[IMX8MP_SYS_PLL1_80M_CG] = imx_clk_hw_gate("sys_pll1_80m_cg", "sys_pll1_bypass", anatop_base + 0x94, 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) hws[IMX8MP_SYS_PLL1_100M_CG] = imx_clk_hw_gate("sys_pll1_100m_cg", "sys_pll1_bypass", anatop_base + 0x94, 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) hws[IMX8MP_SYS_PLL1_133M_CG] = imx_clk_hw_gate("sys_pll1_133m_cg", "sys_pll1_bypass", anatop_base + 0x94, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) hws[IMX8MP_SYS_PLL1_160M_CG] = imx_clk_hw_gate("sys_pll1_160m_cg", "sys_pll1_bypass", anatop_base + 0x94, 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) hws[IMX8MP_SYS_PLL1_200M_CG] = imx_clk_hw_gate("sys_pll1_200m_cg", "sys_pll1_bypass", anatop_base + 0x94, 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) hws[IMX8MP_SYS_PLL1_266M_CG] = imx_clk_hw_gate("sys_pll1_266m_cg", "sys_pll1_bypass", anatop_base + 0x94, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) hws[IMX8MP_SYS_PLL1_400M_CG] = imx_clk_hw_gate("sys_pll1_400m_cg", "sys_pll1_bypass", anatop_base + 0x94, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) hws[IMX8MP_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1_bypass", anatop_base + 0x94, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) hws[IMX8MP_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_40m_cg", 1, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) hws[IMX8MP_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_80m_cg", 1, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) hws[IMX8MP_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_100m_cg", 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) hws[IMX8MP_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_133m_cg", 1, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) hws[IMX8MP_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_160m_cg", 1, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) hws[IMX8MP_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_200m_cg", 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) hws[IMX8MP_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_266m_cg", 1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) hws[IMX8MP_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_400m_cg", 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) hws[IMX8MP_SYS_PLL1_800M] = imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) hws[IMX8MP_SYS_PLL2_50M_CG] = imx_clk_hw_gate("sys_pll2_50m_cg", "sys_pll2_bypass", anatop_base + 0x104, 27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) hws[IMX8MP_SYS_PLL2_100M_CG] = imx_clk_hw_gate("sys_pll2_100m_cg", "sys_pll2_bypass", anatop_base + 0x104, 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) hws[IMX8MP_SYS_PLL2_125M_CG] = imx_clk_hw_gate("sys_pll2_125m_cg", "sys_pll2_bypass", anatop_base + 0x104, 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) hws[IMX8MP_SYS_PLL2_166M_CG] = imx_clk_hw_gate("sys_pll2_166m_cg", "sys_pll2_bypass", anatop_base + 0x104, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) hws[IMX8MP_SYS_PLL2_200M_CG] = imx_clk_hw_gate("sys_pll2_200m_cg", "sys_pll2_bypass", anatop_base + 0x104, 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) hws[IMX8MP_SYS_PLL2_250M_CG] = imx_clk_hw_gate("sys_pll2_250m_cg", "sys_pll2_bypass", anatop_base + 0x104, 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) hws[IMX8MP_SYS_PLL2_333M_CG] = imx_clk_hw_gate("sys_pll2_333m_cg", "sys_pll2_bypass", anatop_base + 0x104, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) hws[IMX8MP_SYS_PLL2_500M_CG] = imx_clk_hw_gate("sys_pll2_500m_cg", "sys_pll2_bypass", anatop_base + 0x104, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) hws[IMX8MP_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2_bypass", anatop_base + 0x104, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) hws[IMX8MP_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_50m_cg", 1, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) hws[IMX8MP_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_100m_cg", 1, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) hws[IMX8MP_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_125m_cg", 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) hws[IMX8MP_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_166m_cg", 1, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) hws[IMX8MP_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_200m_cg", 1, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) hws[IMX8MP_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_250m_cg", 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) hws[IMX8MP_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_333m_cg", 1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) hws[IMX8MP_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) hws[IMX8MP_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) hws[IMX8MP_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels, ccm_base + 0x8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) hws[IMX8MP_CLK_A53_CG] = hws[IMX8MP_CLK_A53_DIV];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) hws[IMX8MP_CLK_M7_CORE] = imx8m_clk_hw_composite_core("m7_core", imx8mp_m7_sels, ccm_base + 0x8080);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) hws[IMX8MP_CLK_ML_CORE] = imx8m_clk_hw_composite_core("ml_core", imx8mp_ml_sels, ccm_base + 0x8100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) hws[IMX8MP_CLK_GPU3D_CORE] = imx8m_clk_hw_composite_core("gpu3d_core", imx8mp_gpu3d_core_sels, ccm_base + 0x8180);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) hws[IMX8MP_CLK_GPU3D_SHADER_CORE] = imx8m_clk_hw_composite("gpu3d_shader_core", imx8mp_gpu3d_shader_sels, ccm_base + 0x8200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) hws[IMX8MP_CLK_GPU2D_CORE] = imx8m_clk_hw_composite("gpu2d_core", imx8mp_gpu2d_sels, ccm_base + 0x8280);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) hws[IMX8MP_CLK_AUDIO_AXI] = imx8m_clk_hw_composite("audio_axi", imx8mp_audio_axi_sels, ccm_base + 0x8300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) hws[IMX8MP_CLK_AUDIO_AXI_SRC] = hws[IMX8MP_CLK_AUDIO_AXI];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) hws[IMX8MP_CLK_HSIO_AXI] = imx8m_clk_hw_composite("hsio_axi", imx8mp_hsio_axi_sels, ccm_base + 0x8380);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) hws[IMX8MP_CLK_MEDIA_ISP] = imx8m_clk_hw_composite("media_isp", imx8mp_media_isp_sels, ccm_base + 0x8400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* CORE SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) hws[IMX8MP_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core", ccm_base + 0x9880, 24, 1, imx8mp_a53_core_sels, ARRAY_SIZE(imx8mp_a53_core_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) hws[IMX8MP_CLK_MAIN_AXI] = imx8m_clk_hw_composite_bus_critical("main_axi", imx8mp_main_axi_sels, ccm_base + 0x8800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) hws[IMX8MP_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi", imx8mp_enet_axi_sels, ccm_base + 0x8880);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) hws[IMX8MP_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_bus_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, ccm_base + 0x8900);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) hws[IMX8MP_CLK_VPU_BUS] = imx8m_clk_hw_composite_bus("vpu_bus", imx8mp_vpu_bus_sels, ccm_base + 0x8980);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) hws[IMX8MP_CLK_MEDIA_AXI] = imx8m_clk_hw_composite_bus("media_axi", imx8mp_media_axi_sels, ccm_base + 0x8a00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) hws[IMX8MP_CLK_MEDIA_APB] = imx8m_clk_hw_composite_bus("media_apb", imx8mp_media_apb_sels, ccm_base + 0x8a80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) hws[IMX8MP_CLK_HDMI_APB] = imx8m_clk_hw_composite_bus("hdmi_apb", imx8mp_media_apb_sels, ccm_base + 0x8b00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) hws[IMX8MP_CLK_HDMI_AXI] = imx8m_clk_hw_composite_bus("hdmi_axi", imx8mp_media_axi_sels, ccm_base + 0x8b80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) hws[IMX8MP_CLK_GPU_AXI] = imx8m_clk_hw_composite_bus("gpu_axi", imx8mp_gpu_axi_sels, ccm_base + 0x8c00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) hws[IMX8MP_CLK_GPU_AHB] = imx8m_clk_hw_composite_bus("gpu_ahb", imx8mp_gpu_ahb_sels, ccm_base + 0x8c80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) hws[IMX8MP_CLK_NOC] = imx8m_clk_hw_composite_bus_critical("noc", imx8mp_noc_sels, ccm_base + 0x8d00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) hws[IMX8MP_CLK_NOC_IO] = imx8m_clk_hw_composite_bus_critical("noc_io", imx8mp_noc_io_sels, ccm_base + 0x8d80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) hws[IMX8MP_CLK_ML_AXI] = imx8m_clk_hw_composite_bus("ml_axi", imx8mp_ml_axi_sels, ccm_base + 0x8e00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) hws[IMX8MP_CLK_ML_AHB] = imx8m_clk_hw_composite_bus("ml_ahb", imx8mp_ml_ahb_sels, ccm_base + 0x8e80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) hws[IMX8MP_CLK_AHB] = imx8m_clk_hw_composite_bus_critical("ahb_root", imx8mp_ahb_sels, ccm_base + 0x9000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) hws[IMX8MP_CLK_AUDIO_AHB] = imx8m_clk_hw_composite_bus("audio_ahb", imx8mp_audio_ahb_sels, ccm_base + 0x9100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) hws[IMX8MP_CLK_MIPI_DSI_ESC_RX] = imx8m_clk_hw_composite_bus("mipi_dsi_esc_rx", imx8mp_mipi_dsi_esc_rx_sels, ccm_base + 0x9200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) hws[IMX8MP_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb_root", ccm_base + 0x9080, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) hws[IMX8MP_CLK_IPG_AUDIO_ROOT] = imx_clk_hw_divider2("ipg_audio_root", "audio_ahb", ccm_base + 0x9180, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) hws[IMX8MP_CLK_DRAM_ALT] = imx8m_clk_hw_composite("dram_alt", imx8mp_dram_alt_sels, ccm_base + 0xa000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) hws[IMX8MP_CLK_DRAM_APB] = imx8m_clk_hw_composite_critical("dram_apb", imx8mp_dram_apb_sels, ccm_base + 0xa080);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) hws[IMX8MP_CLK_VPU_G1] = imx8m_clk_hw_composite("vpu_g1", imx8mp_vpu_g1_sels, ccm_base + 0xa100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) hws[IMX8MP_CLK_VPU_G2] = imx8m_clk_hw_composite("vpu_g2", imx8mp_vpu_g2_sels, ccm_base + 0xa180);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) hws[IMX8MP_CLK_CAN1] = imx8m_clk_hw_composite("can1", imx8mp_can1_sels, ccm_base + 0xa200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) hws[IMX8MP_CLK_CAN2] = imx8m_clk_hw_composite("can2", imx8mp_can2_sels, ccm_base + 0xa280);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) hws[IMX8MP_CLK_PCIE_PHY] = imx8m_clk_hw_composite("pcie_phy", imx8mp_pcie_phy_sels, ccm_base + 0xa380);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) hws[IMX8MP_CLK_PCIE_AUX] = imx8m_clk_hw_composite("pcie_aux", imx8mp_pcie_aux_sels, ccm_base + 0xa400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) hws[IMX8MP_CLK_I2C5] = imx8m_clk_hw_composite("i2c5", imx8mp_i2c5_sels, ccm_base + 0xa480);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) hws[IMX8MP_CLK_I2C6] = imx8m_clk_hw_composite("i2c6", imx8mp_i2c6_sels, ccm_base + 0xa500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) hws[IMX8MP_CLK_SAI1] = imx8m_clk_hw_composite("sai1", imx8mp_sai1_sels, ccm_base + 0xa580);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) hws[IMX8MP_CLK_SAI2] = imx8m_clk_hw_composite("sai2", imx8mp_sai2_sels, ccm_base + 0xa600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) hws[IMX8MP_CLK_SAI3] = imx8m_clk_hw_composite("sai3", imx8mp_sai3_sels, ccm_base + 0xa680);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) hws[IMX8MP_CLK_SAI4] = imx8m_clk_hw_composite("sai4", imx8mp_sai4_sels, ccm_base + 0xa700);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) hws[IMX8MP_CLK_SAI5] = imx8m_clk_hw_composite("sai5", imx8mp_sai5_sels, ccm_base + 0xa780);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) hws[IMX8MP_CLK_SAI6] = imx8m_clk_hw_composite("sai6", imx8mp_sai6_sels, ccm_base + 0xa800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) hws[IMX8MP_CLK_ENET_QOS] = imx8m_clk_hw_composite("enet_qos", imx8mp_enet_qos_sels, ccm_base + 0xa880);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) hws[IMX8MP_CLK_ENET_QOS_TIMER] = imx8m_clk_hw_composite("enet_qos_timer", imx8mp_enet_qos_timer_sels, ccm_base + 0xa900);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) hws[IMX8MP_CLK_ENET_REF] = imx8m_clk_hw_composite("enet_ref", imx8mp_enet_ref_sels, ccm_base + 0xa980);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) hws[IMX8MP_CLK_ENET_TIMER] = imx8m_clk_hw_composite("enet_timer", imx8mp_enet_timer_sels, ccm_base + 0xaa00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) hws[IMX8MP_CLK_ENET_PHY_REF] = imx8m_clk_hw_composite("enet_phy_ref", imx8mp_enet_phy_ref_sels, ccm_base + 0xaa80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) hws[IMX8MP_CLK_NAND] = imx8m_clk_hw_composite("nand", imx8mp_nand_sels, ccm_base + 0xab00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) hws[IMX8MP_CLK_QSPI] = imx8m_clk_hw_composite("qspi", imx8mp_qspi_sels, ccm_base + 0xab80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) hws[IMX8MP_CLK_USDHC1] = imx8m_clk_hw_composite("usdhc1", imx8mp_usdhc1_sels, ccm_base + 0xac00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) hws[IMX8MP_CLK_USDHC2] = imx8m_clk_hw_composite("usdhc2", imx8mp_usdhc2_sels, ccm_base + 0xac80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) hws[IMX8MP_CLK_I2C1] = imx8m_clk_hw_composite("i2c1", imx8mp_i2c1_sels, ccm_base + 0xad00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) hws[IMX8MP_CLK_I2C2] = imx8m_clk_hw_composite("i2c2", imx8mp_i2c2_sels, ccm_base + 0xad80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) hws[IMX8MP_CLK_I2C3] = imx8m_clk_hw_composite("i2c3", imx8mp_i2c3_sels, ccm_base + 0xae00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) hws[IMX8MP_CLK_I2C4] = imx8m_clk_hw_composite("i2c4", imx8mp_i2c4_sels, ccm_base + 0xae80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) hws[IMX8MP_CLK_UART1] = imx8m_clk_hw_composite("uart1", imx8mp_uart1_sels, ccm_base + 0xaf00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) hws[IMX8MP_CLK_UART2] = imx8m_clk_hw_composite("uart2", imx8mp_uart2_sels, ccm_base + 0xaf80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) hws[IMX8MP_CLK_UART3] = imx8m_clk_hw_composite("uart3", imx8mp_uart3_sels, ccm_base + 0xb000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) hws[IMX8MP_CLK_UART4] = imx8m_clk_hw_composite("uart4", imx8mp_uart4_sels, ccm_base + 0xb080);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) hws[IMX8MP_CLK_USB_CORE_REF] = imx8m_clk_hw_composite("usb_core_ref", imx8mp_usb_core_ref_sels, ccm_base + 0xb100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) hws[IMX8MP_CLK_USB_PHY_REF] = imx8m_clk_hw_composite("usb_phy_ref", imx8mp_usb_phy_ref_sels, ccm_base + 0xb180);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) hws[IMX8MP_CLK_GIC] = imx8m_clk_hw_composite_critical("gic", imx8mp_gic_sels, ccm_base + 0xb200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) hws[IMX8MP_CLK_ECSPI1] = imx8m_clk_hw_composite("ecspi1", imx8mp_ecspi1_sels, ccm_base + 0xb280);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) hws[IMX8MP_CLK_ECSPI2] = imx8m_clk_hw_composite("ecspi2", imx8mp_ecspi2_sels, ccm_base + 0xb300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) hws[IMX8MP_CLK_PWM1] = imx8m_clk_hw_composite("pwm1", imx8mp_pwm1_sels, ccm_base + 0xb380);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) hws[IMX8MP_CLK_PWM2] = imx8m_clk_hw_composite("pwm2", imx8mp_pwm2_sels, ccm_base + 0xb400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) hws[IMX8MP_CLK_PWM3] = imx8m_clk_hw_composite("pwm3", imx8mp_pwm3_sels, ccm_base + 0xb480);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) hws[IMX8MP_CLK_PWM4] = imx8m_clk_hw_composite("pwm4", imx8mp_pwm4_sels, ccm_base + 0xb500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) hws[IMX8MP_CLK_GPT1] = imx8m_clk_hw_composite("gpt1", imx8mp_gpt1_sels, ccm_base + 0xb580);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) hws[IMX8MP_CLK_GPT2] = imx8m_clk_hw_composite("gpt2", imx8mp_gpt2_sels, ccm_base + 0xb600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) hws[IMX8MP_CLK_GPT3] = imx8m_clk_hw_composite("gpt3", imx8mp_gpt3_sels, ccm_base + 0xb680);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) hws[IMX8MP_CLK_GPT4] = imx8m_clk_hw_composite("gpt4", imx8mp_gpt4_sels, ccm_base + 0xb700);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) hws[IMX8MP_CLK_GPT5] = imx8m_clk_hw_composite("gpt5", imx8mp_gpt5_sels, ccm_base + 0xb780);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) hws[IMX8MP_CLK_GPT6] = imx8m_clk_hw_composite("gpt6", imx8mp_gpt6_sels, ccm_base + 0xb800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) hws[IMX8MP_CLK_WDOG] = imx8m_clk_hw_composite("wdog", imx8mp_wdog_sels, ccm_base + 0xb900);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) hws[IMX8MP_CLK_WRCLK] = imx8m_clk_hw_composite("wrclk", imx8mp_wrclk_sels, ccm_base + 0xb980);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) hws[IMX8MP_CLK_IPP_DO_CLKO1] = imx8m_clk_hw_composite("ipp_do_clko1", imx8mp_ipp_do_clko1_sels, ccm_base + 0xba00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) hws[IMX8MP_CLK_IPP_DO_CLKO2] = imx8m_clk_hw_composite("ipp_do_clko2", imx8mp_ipp_do_clko2_sels, ccm_base + 0xba80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) hws[IMX8MP_CLK_HDMI_FDCC_TST] = imx8m_clk_hw_composite("hdmi_fdcc_tst", imx8mp_hdmi_fdcc_tst_sels, ccm_base + 0xbb00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) hws[IMX8MP_CLK_HDMI_24M] = imx8m_clk_hw_composite("hdmi_24m", imx8mp_hdmi_24m_sels, ccm_base + 0xbb80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) hws[IMX8MP_CLK_HDMI_REF_266M] = imx8m_clk_hw_composite("hdmi_ref_266m", imx8mp_hdmi_ref_266m_sels, ccm_base + 0xbc00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) hws[IMX8MP_CLK_USDHC3] = imx8m_clk_hw_composite("usdhc3", imx8mp_usdhc3_sels, ccm_base + 0xbc80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) hws[IMX8MP_CLK_MEDIA_CAM1_PIX] = imx8m_clk_hw_composite("media_cam1_pix", imx8mp_media_cam1_pix_sels, ccm_base + 0xbd00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF] = imx8m_clk_hw_composite("media_mipi_phy1_ref", imx8mp_media_mipi_phy1_ref_sels, ccm_base + 0xbd80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) hws[IMX8MP_CLK_MEDIA_DISP1_PIX] = imx8m_clk_hw_composite("media_disp1_pix", imx8mp_media_disp1_pix_sels, ccm_base + 0xbe00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) hws[IMX8MP_CLK_MEDIA_CAM2_PIX] = imx8m_clk_hw_composite("media_cam2_pix", imx8mp_media_cam2_pix_sels, ccm_base + 0xbe80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) hws[IMX8MP_CLK_MEDIA_LDB] = imx8m_clk_hw_composite("media_ldb", imx8mp_media_ldb_sels, ccm_base + 0xbf00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) hws[IMX8MP_CLK_MEMREPAIR] = imx8m_clk_hw_composite_critical("mem_repair", imx8mp_memrepair_sels, ccm_base + 0xbf80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) hws[IMX8MP_CLK_PCIE2_CTRL] = imx8m_clk_hw_composite("pcie2_ctrl", imx8mp_pcie2_ctrl_sels, ccm_base + 0xc000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) hws[IMX8MP_CLK_PCIE2_PHY] = imx8m_clk_hw_composite("pcie2_phy", imx8mp_pcie2_phy_sels, ccm_base + 0xc080);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) hws[IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE] = imx8m_clk_hw_composite("media_mipi_test_byte", imx8mp_media_mipi_test_byte_sels, ccm_base + 0xc100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) hws[IMX8MP_CLK_ECSPI3] = imx8m_clk_hw_composite("ecspi3", imx8mp_ecspi3_sels, ccm_base + 0xc180);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) hws[IMX8MP_CLK_PDM] = imx8m_clk_hw_composite("pdm", imx8mp_pdm_sels, ccm_base + 0xc200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) hws[IMX8MP_CLK_VPU_VC8000E] = imx8m_clk_hw_composite("vpu_vc8000e", imx8mp_vpu_vc8000e_sels, ccm_base + 0xc280);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) hws[IMX8MP_CLK_SAI7] = imx8m_clk_hw_composite("sai7", imx8mp_sai7_sels, ccm_base + 0xc300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) hws[IMX8MP_CLK_DRAM_ALT_ROOT] = imx_clk_hw_fixed_factor("dram_alt_root", "dram_alt", 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) hws[IMX8MP_CLK_DRAM_CORE] = imx_clk_hw_mux2_flags("dram_core_clk", ccm_base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) hws[IMX8MP_CLK_DRAM1_ROOT] = imx_clk_hw_gate4_flags("dram1_root_clk", "dram_core_clk", ccm_base + 0x4050, 0, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) hws[IMX8MP_CLK_ECSPI1_ROOT] = imx_clk_hw_gate4("ecspi1_root_clk", "ecspi1", ccm_base + 0x4070, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) hws[IMX8MP_CLK_ECSPI2_ROOT] = imx_clk_hw_gate4("ecspi2_root_clk", "ecspi2", ccm_base + 0x4080, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) hws[IMX8MP_CLK_ECSPI3_ROOT] = imx_clk_hw_gate4("ecspi3_root_clk", "ecspi3", ccm_base + 0x4090, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) hws[IMX8MP_CLK_ENET1_ROOT] = imx_clk_hw_gate4("enet1_root_clk", "enet_axi", ccm_base + 0x40a0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) hws[IMX8MP_CLK_GPIO1_ROOT] = imx_clk_hw_gate4("gpio1_root_clk", "ipg_root", ccm_base + 0x40b0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) hws[IMX8MP_CLK_GPIO2_ROOT] = imx_clk_hw_gate4("gpio2_root_clk", "ipg_root", ccm_base + 0x40c0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) hws[IMX8MP_CLK_GPIO3_ROOT] = imx_clk_hw_gate4("gpio3_root_clk", "ipg_root", ccm_base + 0x40d0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) hws[IMX8MP_CLK_GPIO4_ROOT] = imx_clk_hw_gate4("gpio4_root_clk", "ipg_root", ccm_base + 0x40e0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) hws[IMX8MP_CLK_GPIO5_ROOT] = imx_clk_hw_gate4("gpio5_root_clk", "ipg_root", ccm_base + 0x40f0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) hws[IMX8MP_CLK_GPT1_ROOT] = imx_clk_hw_gate4("gpt1_root_clk", "gpt1", ccm_base + 0x4100, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) hws[IMX8MP_CLK_GPT2_ROOT] = imx_clk_hw_gate4("gpt2_root_clk", "gpt2", ccm_base + 0x4110, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) hws[IMX8MP_CLK_GPT3_ROOT] = imx_clk_hw_gate4("gpt3_root_clk", "gpt3", ccm_base + 0x4120, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) hws[IMX8MP_CLK_GPT4_ROOT] = imx_clk_hw_gate4("gpt4_root_clk", "gpt4", ccm_base + 0x4130, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) hws[IMX8MP_CLK_GPT5_ROOT] = imx_clk_hw_gate4("gpt5_root_clk", "gpt5", ccm_base + 0x4140, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) hws[IMX8MP_CLK_GPT6_ROOT] = imx_clk_hw_gate4("gpt6_root_clk", "gpt6", ccm_base + 0x4150, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) hws[IMX8MP_CLK_I2C1_ROOT] = imx_clk_hw_gate4("i2c1_root_clk", "i2c1", ccm_base + 0x4170, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) hws[IMX8MP_CLK_I2C2_ROOT] = imx_clk_hw_gate4("i2c2_root_clk", "i2c2", ccm_base + 0x4180, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) hws[IMX8MP_CLK_I2C3_ROOT] = imx_clk_hw_gate4("i2c3_root_clk", "i2c3", ccm_base + 0x4190, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) hws[IMX8MP_CLK_I2C4_ROOT] = imx_clk_hw_gate4("i2c4_root_clk", "i2c4", ccm_base + 0x41a0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) hws[IMX8MP_CLK_MU_ROOT] = imx_clk_hw_gate4("mu_root_clk", "ipg_root", ccm_base + 0x4210, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) hws[IMX8MP_CLK_OCOTP_ROOT] = imx_clk_hw_gate4("ocotp_root_clk", "ipg_root", ccm_base + 0x4220, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) hws[IMX8MP_CLK_PCIE_ROOT] = imx_clk_hw_gate4("pcie_root_clk", "pcie_aux", ccm_base + 0x4250, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) hws[IMX8MP_CLK_PWM1_ROOT] = imx_clk_hw_gate4("pwm1_root_clk", "pwm1", ccm_base + 0x4280, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) hws[IMX8MP_CLK_PWM2_ROOT] = imx_clk_hw_gate4("pwm2_root_clk", "pwm2", ccm_base + 0x4290, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) hws[IMX8MP_CLK_PWM3_ROOT] = imx_clk_hw_gate4("pwm3_root_clk", "pwm3", ccm_base + 0x42a0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) hws[IMX8MP_CLK_PWM4_ROOT] = imx_clk_hw_gate4("pwm4_root_clk", "pwm4", ccm_base + 0x42b0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) hws[IMX8MP_CLK_QOS_ROOT] = imx_clk_hw_gate4("qos_root_clk", "ipg_root", ccm_base + 0x42c0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) hws[IMX8MP_CLK_QOS_ENET_ROOT] = imx_clk_hw_gate4("qos_enet_root_clk", "ipg_root", ccm_base + 0x42e0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) hws[IMX8MP_CLK_QSPI_ROOT] = imx_clk_hw_gate4("qspi_root_clk", "qspi", ccm_base + 0x42f0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) hws[IMX8MP_CLK_NAND_ROOT] = imx_clk_hw_gate2_shared2("nand_root_clk", "nand", ccm_base + 0x4300, 0, &share_count_nand);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) hws[IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_hw_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus", ccm_base + 0x4300, 0, &share_count_nand);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) hws[IMX8MP_CLK_I2C5_ROOT] = imx_clk_hw_gate2("i2c5_root_clk", "i2c5", ccm_base + 0x4330, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) hws[IMX8MP_CLK_I2C6_ROOT] = imx_clk_hw_gate2("i2c6_root_clk", "i2c6", ccm_base + 0x4340, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) hws[IMX8MP_CLK_CAN1_ROOT] = imx_clk_hw_gate2("can1_root_clk", "can1", ccm_base + 0x4350, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) hws[IMX8MP_CLK_CAN2_ROOT] = imx_clk_hw_gate2("can2_root_clk", "can2", ccm_base + 0x4360, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) hws[IMX8MP_CLK_SDMA1_ROOT] = imx_clk_hw_gate4("sdma1_root_clk", "ipg_root", ccm_base + 0x43a0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) hws[IMX8MP_CLK_ENET_QOS_ROOT] = imx_clk_hw_gate4("enet_qos_root_clk", "sim_enet_root_clk", ccm_base + 0x43b0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) hws[IMX8MP_CLK_SIM_ENET_ROOT] = imx_clk_hw_gate4("sim_enet_root_clk", "enet_axi", ccm_base + 0x4400, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) hws[IMX8MP_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk", "gpu2d_core", ccm_base + 0x4450, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) hws[IMX8MP_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk", "gpu3d_core", ccm_base + 0x4460, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) hws[IMX8MP_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk", "ipg_root", ccm_base + 0x4470, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) hws[IMX8MP_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk", "uart1", ccm_base + 0x4490, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) hws[IMX8MP_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", ccm_base + 0x44a0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) hws[IMX8MP_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", ccm_base + 0x44b0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) hws[IMX8MP_CLK_UART4_ROOT] = imx_clk_hw_gate4("uart4_root_clk", "uart4", ccm_base + 0x44c0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) hws[IMX8MP_CLK_USB_ROOT] = imx_clk_hw_gate4("usb_root_clk", "osc_32k", ccm_base + 0x44d0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) hws[IMX8MP_CLK_USB_PHY_ROOT] = imx_clk_hw_gate4("usb_phy_root_clk", "usb_phy_ref", ccm_base + 0x44f0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) hws[IMX8MP_CLK_USDHC1_ROOT] = imx_clk_hw_gate4("usdhc1_root_clk", "usdhc1", ccm_base + 0x4510, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) hws[IMX8MP_CLK_USDHC2_ROOT] = imx_clk_hw_gate4("usdhc2_root_clk", "usdhc2", ccm_base + 0x4520, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) hws[IMX8MP_CLK_WDOG1_ROOT] = imx_clk_hw_gate4("wdog1_root_clk", "wdog", ccm_base + 0x4530, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) hws[IMX8MP_CLK_WDOG2_ROOT] = imx_clk_hw_gate4("wdog2_root_clk", "wdog", ccm_base + 0x4540, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) hws[IMX8MP_CLK_WDOG3_ROOT] = imx_clk_hw_gate4("wdog3_root_clk", "wdog", ccm_base + 0x4550, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) hws[IMX8MP_CLK_VPU_G1_ROOT] = imx_clk_hw_gate4("vpu_g1_root_clk", "vpu_g1", ccm_base + 0x4560, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) hws[IMX8MP_CLK_GPU_ROOT] = imx_clk_hw_gate4("gpu_root_clk", "gpu_axi", ccm_base + 0x4570, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) hws[IMX8MP_CLK_VPU_VC8KE_ROOT] = imx_clk_hw_gate4("vpu_vc8ke_root_clk", "vpu_vc8000e", ccm_base + 0x4590, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) hws[IMX8MP_CLK_VPU_G2_ROOT] = imx_clk_hw_gate4("vpu_g2_root_clk", "vpu_g2", ccm_base + 0x45a0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) hws[IMX8MP_CLK_NPU_ROOT] = imx_clk_hw_gate4("npu_root_clk", "ml_core", ccm_base + 0x45b0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) hws[IMX8MP_CLK_HSIO_ROOT] = imx_clk_hw_gate4("hsio_root_clk", "ipg_root", ccm_base + 0x45c0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) hws[IMX8MP_CLK_MEDIA_APB_ROOT] = imx_clk_hw_gate2_shared2("media_apb_root_clk", "media_apb", ccm_base + 0x45d0, 0, &share_count_media);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) hws[IMX8MP_CLK_MEDIA_AXI_ROOT] = imx_clk_hw_gate2_shared2("media_axi_root_clk", "media_axi", ccm_base + 0x45d0, 0, &share_count_media);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) hws[IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_cam1_pix_root_clk", "media_cam1_pix", ccm_base + 0x45d0, 0, &share_count_media);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) hws[IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_cam2_pix_root_clk", "media_cam2_pix", ccm_base + 0x45d0, 0, &share_count_media);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) hws[IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_disp1_pix_root_clk", "media_disp1_pix", ccm_base + 0x45d0, 0, &share_count_media);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) hws[IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_disp2_pix_root_clk", "media_disp2_pix", ccm_base + 0x45d0, 0, &share_count_media);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) hws[IMX8MP_CLK_MEDIA_ISP_ROOT] = imx_clk_hw_gate2_shared2("media_isp_root_clk", "media_isp", ccm_base + 0x45d0, 0, &share_count_media);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) hws[IMX8MP_CLK_USDHC3_ROOT] = imx_clk_hw_gate4("usdhc3_root_clk", "usdhc3", ccm_base + 0x45e0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) hws[IMX8MP_CLK_HDMI_ROOT] = imx_clk_hw_gate4("hdmi_root_clk", "hdmi_axi", ccm_base + 0x45f0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) hws[IMX8MP_CLK_TSENSOR_ROOT] = imx_clk_hw_gate4("tsensor_root_clk", "ipg_root", ccm_base + 0x4620, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) hws[IMX8MP_CLK_VPU_ROOT] = imx_clk_hw_gate4("vpu_root_clk", "vpu_bus", ccm_base + 0x4630, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) hws[IMX8MP_CLK_AUDIO_ROOT] = imx_clk_hw_gate4("audio_root_clk", "ipg_root", ccm_base + 0x4650, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) hws[IMX8MP_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) hws[IMX8MP_CLK_A53_CORE]->clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) hws[IMX8MP_CLK_A53_CORE]->clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) hws[IMX8MP_ARM_PLL_OUT]->clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) hws[IMX8MP_CLK_A53_DIV]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) imx_check_clk_hws(hws, IMX8MP_CLK_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) imx_register_uart_clocks(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static const struct of_device_id imx8mp_clk_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) { .compatible = "fsl,imx8mp-ccm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) { /* Sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) MODULE_DEVICE_TABLE(of, imx8mp_clk_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static struct platform_driver imx8mp_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .probe = imx8mp_clocks_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .name = "imx8mp-ccm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * Disable bind attributes: clocks are not removed and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * reloading the driver will crash or break devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .of_match_table = of_match_ptr(imx8mp_clk_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) module_platform_driver(imx8mp_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) MODULE_DESCRIPTION("NXP i.MX8MP clock driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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