^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2017-2018 NXP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <dt-bindings/clock/imx8mm-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static u32 share_count_sai1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static u32 share_count_sai2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static u32 share_count_sai3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static u32 share_count_sai4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static u32 share_count_sai5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static u32 share_count_sai6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static u32 share_count_disp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static u32 share_count_pdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static u32 share_count_nand;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static const char *pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static const char *audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static const char *audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static const char *video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static const char *gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const char *vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* CCM ROOT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static const char *imx8mm_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static const char * const imx8mm_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static const char *imx8mm_m4_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m", "sys_pll1_266m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const char *imx8mm_vpu_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "vpu_pll_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static const char *imx8mm_gpu3d_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", "sys_pll3_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static const char *imx8mm_gpu2d_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", "sys_pll3_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static const char *imx8mm_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m", "sys_pll2_250m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", "sys_pll1_100m",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static const char *imx8mm_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static const char *imx8mm_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static const char *imx8mm_vpu_bus_sels[] = {"osc_24m", "sys_pll1_800m", "vpu_pll_out", "audio_pll2_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "sys_pll3_out", "sys_pll2_1000m", "sys_pll2_200m", "sys_pll1_100m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static const char *imx8mm_disp_axi_sels[] = {"osc_24m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll3_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) "sys_pll1_40m", "audio_pll2_out", "clk_ext1", "clk_ext4", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static const char *imx8mm_disp_apb_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll1_800m", "sys_pll3_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) "sys_pll1_40m", "audio_pll2_out", "clk_ext1", "clk_ext3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static const char *imx8mm_disp_rtrm_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll2_200m", "sys_pll2_1000m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "audio_pll1_out", "video_pll1_out", "clk_ext2", "clk_ext3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static const char *imx8mm_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) "sys_pll2_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static const char *imx8mm_gpu_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const char *imx8mm_gpu_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const char *imx8mm_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "sys_pll2_500m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const char *imx8mm_noc_apb_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll3_out", "sys_pll2_333m", "sys_pll2_200m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static const char *imx8mm_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static const char *imx8mm_audio_ahb_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_1000m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static const char *imx8mm_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m", "sys_pll2_500m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) "sys_pll2_1000m", "sys_pll3_out", "audio_pll1_out", "sys_pll1_266m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const char *imx8mm_dram_apb_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const char *imx8mm_vpu_g1_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", "sys_pll2_1000m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "sys_pll1_100m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const char *imx8mm_vpu_g2_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", "sys_pll2_1000m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) "sys_pll1_100m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static const char *imx8mm_disp_dtrc_sels[] = {"osc_24m", "dummy", "sys_pll1_800m", "sys_pll2_1000m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "sys_pll1_160m", "video_pll1_out", "sys_pll3_out", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static const char *imx8mm_disp_dc8000_sels[] = {"osc_24m", "dummy", "sys_pll1_800m", "sys_pll2_1000m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) "sys_pll1_160m", "video_pll1_out", "sys_pll3_out", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const char *imx8mm_pcie1_ctrl_sels[] = {"osc_24m", "sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "sys_pll1_800m", "sys_pll2_500m", "sys_pll2_333m", "sys_pll3_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const char *imx8mm_pcie1_phy_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll2_500m", "clk_ext1", "clk_ext2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) "clk_ext3", "clk_ext4", "sys_pll1_400m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const char *imx8mm_pcie1_aux_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m", "sys_pll3_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_160m", "sys_pll1_200m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const char *imx8mm_dc_pixel_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const char *imx8mm_lcdif_pixel_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const char *imx8mm_sai1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) "sys_pll1_133m", "osc_hdmi", "clk_ext1", "clk_ext2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const char *imx8mm_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const char *imx8mm_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const char *imx8mm_sai4_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) "sys_pll1_133m", "osc_hdmi", "clk_ext1", "clk_ext2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const char *imx8mm_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) "sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const char *imx8mm_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const char *imx8mm_spdif1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const char *imx8mm_spdif2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const char *imx8mm_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const char *imx8mm_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "clk_ext3", "clk_ext4", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const char *imx8mm_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const char *imx8mm_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out", "sys_pll1_400m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) "audio_pll2_out", "sys_pll3_out", "sys_pll2_250m", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const char *imx8mm_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const char *imx8mm_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static const char *imx8mm_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const char *imx8mm_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const char *imx8mm_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const char *imx8mm_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static const char *imx8mm_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static const char *imx8mm_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", "sys_pll2_100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) "sys_pll3_out", "clk_ext2", "clk_ext4", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const char *imx8mm_uart2_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", "sys_pll2_100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "sys_pll3_out", "clk_ext2", "clk_ext3", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const char *imx8mm_uart3_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", "sys_pll2_100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) "sys_pll3_out", "clk_ext2", "clk_ext4", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static const char *imx8mm_uart4_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", "sys_pll2_100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) "sys_pll3_out", "clk_ext2", "clk_ext3", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static const char *imx8mm_usb_core_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const char *imx8mm_usb_phy_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const char *imx8mm_gic_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll2_100m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "sys_pll1_800m", "clk_ext2", "clk_ext4", "audio_pll2_out" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const char *imx8mm_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const char *imx8mm_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const char *imx8mm_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static const char *imx8mm_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const char *imx8mm_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const char *imx8mm_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const char *imx8mm_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", "sys_pll1_40m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) "video_pll1_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static const char *imx8mm_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static const char *imx8mm_wrclk_sels[] = {"osc_24m", "sys_pll1_40m", "vpu_pll_out", "sys_pll3_out", "sys_pll2_200m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) "sys_pll1_266m", "sys_pll2_500m", "sys_pll1_100m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static const char *imx8mm_dsi_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const char *imx8mm_dsi_phy_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_100m", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const char *imx8mm_dsi_dbi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_100m", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static const char *imx8mm_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const char *imx8mm_csi1_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const char *imx8mm_csi1_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static const char *imx8mm_csi1_esc_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) "sys_pll2_1000m", "sys_pll3_out", "clk_ext3", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static const char *imx8mm_csi2_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const char *imx8mm_csi2_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const char *imx8mm_csi2_esc_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) "sys_pll2_1000m", "sys_pll3_out", "clk_ext3", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static const char *imx8mm_pcie2_ctrl_sels[] = {"osc_24m", "sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) "sys_pll1_800m", "sys_pll2_500m", "sys_pll2_333m", "sys_pll3_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static const char *imx8mm_pcie2_phy_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll2_500m", "clk_ext1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "clk_ext2", "clk_ext3", "clk_ext4", "sys_pll1_400m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const char *imx8mm_pcie2_aux_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m", "sys_pll3_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_160m", "sys_pll1_200m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const char *imx8mm_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static const char *imx8mm_pdm_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", "sys_pll1_800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) "sys_pll2_1000m", "sys_pll3_out", "clk_ext3", "audio_pll2_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static const char *imx8mm_vpu_h1_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", "sys_pll2_1000m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) "audio_pll2_out", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const char *imx8mm_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "dummy", "sys_pll1_200m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) "audio_pll2_out", "sys_pll2_500m", "vpu_pll", "sys_pll1_80m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const char *imx8mm_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m", "sys_pll2_166m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "osc_32k", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static struct clk_hw_onecell_data *clk_hw_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static struct clk_hw **hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int imx8mm_clocks_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) IMX8MM_CLK_END), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (WARN_ON(!clk_hw_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) clk_hw_data->num = IMX8MM_CLK_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) hws = clk_hw_data->hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) hws[IMX8MM_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) hws[IMX8MM_CLK_24M] = imx_obtain_fixed_clk_hw(np, "osc_24m");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) hws[IMX8MM_CLK_32K] = imx_obtain_fixed_clk_hw(np, "osc_32k");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) hws[IMX8MM_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) hws[IMX8MM_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) hws[IMX8MM_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) hws[IMX8MM_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (WARN_ON(!base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) hws[IMX8MM_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) hws[IMX8MM_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) hws[IMX8MM_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) hws[IMX8MM_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) hws[IMX8MM_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) hws[IMX8MM_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) hws[IMX8MM_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) hws[IMX8MM_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) hws[IMX8MM_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) hws[IMX8MM_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) hws[IMX8MM_VIDEO_PLL1] = imx_clk_hw_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx_1443x_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) hws[IMX8MM_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) hws[IMX8MM_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) hws[IMX8MM_VPU_PLL] = imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx_1416x_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) hws[IMX8MM_ARM_PLL] = imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx_1416x_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) hws[IMX8MM_SYS_PLL1] = imx_clk_hw_fixed("sys_pll1", 800000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) hws[IMX8MM_SYS_PLL2] = imx_clk_hw_fixed("sys_pll2", 1000000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) hws[IMX8MM_SYS_PLL3] = imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx_1416x_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* PLL bypass out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) hws[IMX8MM_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) hws[IMX8MM_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) hws[IMX8MM_VIDEO_PLL1_BYPASS] = imx_clk_hw_mux_flags("video_pll1_bypass", base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) hws[IMX8MM_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) hws[IMX8MM_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) hws[IMX8MM_VPU_PLL_BYPASS] = imx_clk_hw_mux_flags("vpu_pll_bypass", base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) hws[IMX8MM_ARM_PLL_BYPASS] = imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) hws[IMX8MM_SYS_PLL3_BYPASS] = imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* PLL out gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) hws[IMX8MM_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", base, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) hws[IMX8MM_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) hws[IMX8MM_VIDEO_PLL1_OUT] = imx_clk_hw_gate("video_pll1_out", "video_pll1_bypass", base + 0x28, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) hws[IMX8MM_DRAM_PLL_OUT] = imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) hws[IMX8MM_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) hws[IMX8MM_VPU_PLL_OUT] = imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) hws[IMX8MM_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) hws[IMX8MM_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* SYS PLL1 fixed output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) hws[IMX8MM_SYS_PLL1_40M_CG] = imx_clk_hw_gate("sys_pll1_40m_cg", "sys_pll1", base + 0x94, 27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) hws[IMX8MM_SYS_PLL1_80M_CG] = imx_clk_hw_gate("sys_pll1_80m_cg", "sys_pll1", base + 0x94, 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) hws[IMX8MM_SYS_PLL1_100M_CG] = imx_clk_hw_gate("sys_pll1_100m_cg", "sys_pll1", base + 0x94, 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) hws[IMX8MM_SYS_PLL1_133M_CG] = imx_clk_hw_gate("sys_pll1_133m_cg", "sys_pll1", base + 0x94, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) hws[IMX8MM_SYS_PLL1_160M_CG] = imx_clk_hw_gate("sys_pll1_160m_cg", "sys_pll1", base + 0x94, 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) hws[IMX8MM_SYS_PLL1_200M_CG] = imx_clk_hw_gate("sys_pll1_200m_cg", "sys_pll1", base + 0x94, 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) hws[IMX8MM_SYS_PLL1_266M_CG] = imx_clk_hw_gate("sys_pll1_266m_cg", "sys_pll1", base + 0x94, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) hws[IMX8MM_SYS_PLL1_400M_CG] = imx_clk_hw_gate("sys_pll1_400m_cg", "sys_pll1", base + 0x94, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) hws[IMX8MM_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) hws[IMX8MM_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_40m_cg", 1, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) hws[IMX8MM_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_80m_cg", 1, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) hws[IMX8MM_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_100m_cg", 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) hws[IMX8MM_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_133m_cg", 1, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) hws[IMX8MM_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_160m_cg", 1, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) hws[IMX8MM_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_200m_cg", 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) hws[IMX8MM_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_266m_cg", 1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) hws[IMX8MM_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_400m_cg", 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) hws[IMX8MM_SYS_PLL1_800M] = imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* SYS PLL2 fixed output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) hws[IMX8MM_SYS_PLL2_50M_CG] = imx_clk_hw_gate("sys_pll2_50m_cg", "sys_pll2", base + 0x104, 27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) hws[IMX8MM_SYS_PLL2_100M_CG] = imx_clk_hw_gate("sys_pll2_100m_cg", "sys_pll2", base + 0x104, 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) hws[IMX8MM_SYS_PLL2_125M_CG] = imx_clk_hw_gate("sys_pll2_125m_cg", "sys_pll2", base + 0x104, 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) hws[IMX8MM_SYS_PLL2_166M_CG] = imx_clk_hw_gate("sys_pll2_166m_cg", "sys_pll2", base + 0x104, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) hws[IMX8MM_SYS_PLL2_200M_CG] = imx_clk_hw_gate("sys_pll2_200m_cg", "sys_pll2", base + 0x104, 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) hws[IMX8MM_SYS_PLL2_250M_CG] = imx_clk_hw_gate("sys_pll2_250m_cg", "sys_pll2", base + 0x104, 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) hws[IMX8MM_SYS_PLL2_333M_CG] = imx_clk_hw_gate("sys_pll2_333m_cg", "sys_pll2", base + 0x104, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) hws[IMX8MM_SYS_PLL2_500M_CG] = imx_clk_hw_gate("sys_pll2_500m_cg", "sys_pll2", base + 0x104, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) hws[IMX8MM_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) hws[IMX8MM_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_50m_cg", 1, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) hws[IMX8MM_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_100m_cg", 1, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) hws[IMX8MM_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_125m_cg", 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) hws[IMX8MM_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_166m_cg", 1, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) hws[IMX8MM_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_200m_cg", 1, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) hws[IMX8MM_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_250m_cg", 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) hws[IMX8MM_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_333m_cg", 1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) hws[IMX8MM_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) hws[IMX8MM_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (WARN_ON(IS_ERR(base)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Core Slice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) hws[IMX8MM_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mm_a53_sels, base + 0x8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) hws[IMX8MM_CLK_A53_CG] = hws[IMX8MM_CLK_A53_DIV];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) hws[IMX8MM_CLK_A53_SRC] = hws[IMX8MM_CLK_A53_DIV];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) hws[IMX8MM_CLK_M4_CORE] = imx8m_clk_hw_composite_core("arm_m4_core", imx8mm_m4_sels, base + 0x8080);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) hws[IMX8MM_CLK_VPU_CORE] = imx8m_clk_hw_composite_core("vpu_core", imx8mm_vpu_sels, base + 0x8100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) hws[IMX8MM_CLK_GPU3D_CORE] = imx8m_clk_hw_composite_core("gpu3d_core", imx8mm_gpu3d_sels, base + 0x8180);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) hws[IMX8MM_CLK_GPU2D_CORE] = imx8m_clk_hw_composite_core("gpu2d_core", imx8mm_gpu2d_sels, base + 0x8200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* For backwards compatibility */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) hws[IMX8MM_CLK_M4_SRC] = hws[IMX8MM_CLK_M4_CORE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) hws[IMX8MM_CLK_M4_CG] = hws[IMX8MM_CLK_M4_CORE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) hws[IMX8MM_CLK_M4_DIV] = hws[IMX8MM_CLK_M4_CORE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) hws[IMX8MM_CLK_VPU_SRC] = hws[IMX8MM_CLK_VPU_CORE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) hws[IMX8MM_CLK_VPU_CG] = hws[IMX8MM_CLK_VPU_CORE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) hws[IMX8MM_CLK_VPU_DIV] = hws[IMX8MM_CLK_VPU_CORE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) hws[IMX8MM_CLK_GPU3D_SRC] = hws[IMX8MM_CLK_GPU3D_CORE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) hws[IMX8MM_CLK_GPU3D_CG] = hws[IMX8MM_CLK_GPU3D_CORE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) hws[IMX8MM_CLK_GPU3D_DIV] = hws[IMX8MM_CLK_GPU3D_CORE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) hws[IMX8MM_CLK_GPU2D_SRC] = hws[IMX8MM_CLK_GPU2D_CORE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) hws[IMX8MM_CLK_GPU2D_CG] = hws[IMX8MM_CLK_GPU2D_CORE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) hws[IMX8MM_CLK_GPU2D_DIV] = hws[IMX8MM_CLK_GPU2D_CORE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* CORE SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) hws[IMX8MM_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core", base + 0x9880, 24, 1, imx8mm_a53_core_sels, ARRAY_SIZE(imx8mm_a53_core_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* BUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) hws[IMX8MM_CLK_MAIN_AXI] = imx8m_clk_hw_composite_bus_critical("main_axi", imx8mm_main_axi_sels, base + 0x8800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) hws[IMX8MM_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi", imx8mm_enet_axi_sels, base + 0x8880);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) hws[IMX8MM_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_bus_critical("nand_usdhc_bus", imx8mm_nand_usdhc_sels, base + 0x8900);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) hws[IMX8MM_CLK_VPU_BUS] = imx8m_clk_hw_composite_bus("vpu_bus", imx8mm_vpu_bus_sels, base + 0x8980);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) hws[IMX8MM_CLK_DISP_AXI] = imx8m_clk_hw_composite_bus("disp_axi", imx8mm_disp_axi_sels, base + 0x8a00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) hws[IMX8MM_CLK_DISP_APB] = imx8m_clk_hw_composite_bus("disp_apb", imx8mm_disp_apb_sels, base + 0x8a80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) hws[IMX8MM_CLK_DISP_RTRM] = imx8m_clk_hw_composite_bus("disp_rtrm", imx8mm_disp_rtrm_sels, base + 0x8b00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) hws[IMX8MM_CLK_USB_BUS] = imx8m_clk_hw_composite_bus("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) hws[IMX8MM_CLK_GPU_AXI] = imx8m_clk_hw_composite_bus("gpu_axi", imx8mm_gpu_axi_sels, base + 0x8c00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) hws[IMX8MM_CLK_GPU_AHB] = imx8m_clk_hw_composite_bus("gpu_ahb", imx8mm_gpu_ahb_sels, base + 0x8c80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) hws[IMX8MM_CLK_NOC] = imx8m_clk_hw_composite_bus_critical("noc", imx8mm_noc_sels, base + 0x8d00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) hws[IMX8MM_CLK_NOC_APB] = imx8m_clk_hw_composite_bus_critical("noc_apb", imx8mm_noc_apb_sels, base + 0x8d80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* AHB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) hws[IMX8MM_CLK_AHB] = imx8m_clk_hw_composite_bus_critical("ahb", imx8mm_ahb_sels, base + 0x9000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) hws[IMX8MM_CLK_AUDIO_AHB] = imx8m_clk_hw_composite_bus("audio_ahb", imx8mm_audio_ahb_sels, base + 0x9100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* IPG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) hws[IMX8MM_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb", base + 0x9080, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) hws[IMX8MM_CLK_IPG_AUDIO_ROOT] = imx_clk_hw_divider2("ipg_audio_root", "audio_ahb", base + 0x9180, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * DRAM clocks are manipulated from TF-A outside clock framework.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * The fw_managed helper sets GET_RATE_NOCACHE and clears SET_PARENT_GATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * as div value should always be read from hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) hws[IMX8MM_CLK_DRAM_ALT] = imx8m_clk_hw_fw_managed_composite("dram_alt", imx8mm_dram_alt_sels, base + 0xa000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) hws[IMX8MM_CLK_DRAM_APB] = imx8m_clk_hw_fw_managed_composite_critical("dram_apb", imx8mm_dram_apb_sels, base + 0xa080);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) hws[IMX8MM_CLK_VPU_G1] = imx8m_clk_hw_composite("vpu_g1", imx8mm_vpu_g1_sels, base + 0xa100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) hws[IMX8MM_CLK_VPU_G2] = imx8m_clk_hw_composite("vpu_g2", imx8mm_vpu_g2_sels, base + 0xa180);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) hws[IMX8MM_CLK_DISP_DTRC] = imx8m_clk_hw_composite("disp_dtrc", imx8mm_disp_dtrc_sels, base + 0xa200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) hws[IMX8MM_CLK_DISP_DC8000] = imx8m_clk_hw_composite("disp_dc8000", imx8mm_disp_dc8000_sels, base + 0xa280);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) hws[IMX8MM_CLK_PCIE1_CTRL] = imx8m_clk_hw_composite("pcie1_ctrl", imx8mm_pcie1_ctrl_sels, base + 0xa300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) hws[IMX8MM_CLK_PCIE1_PHY] = imx8m_clk_hw_composite("pcie1_phy", imx8mm_pcie1_phy_sels, base + 0xa380);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) hws[IMX8MM_CLK_PCIE1_AUX] = imx8m_clk_hw_composite("pcie1_aux", imx8mm_pcie1_aux_sels, base + 0xa400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) hws[IMX8MM_CLK_DC_PIXEL] = imx8m_clk_hw_composite("dc_pixel", imx8mm_dc_pixel_sels, base + 0xa480);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) hws[IMX8MM_CLK_LCDIF_PIXEL] = imx8m_clk_hw_composite("lcdif_pixel", imx8mm_lcdif_pixel_sels, base + 0xa500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) hws[IMX8MM_CLK_SAI1] = imx8m_clk_hw_composite("sai1", imx8mm_sai1_sels, base + 0xa580);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) hws[IMX8MM_CLK_SAI2] = imx8m_clk_hw_composite("sai2", imx8mm_sai2_sels, base + 0xa600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) hws[IMX8MM_CLK_SAI3] = imx8m_clk_hw_composite("sai3", imx8mm_sai3_sels, base + 0xa680);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) hws[IMX8MM_CLK_SAI4] = imx8m_clk_hw_composite("sai4", imx8mm_sai4_sels, base + 0xa700);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) hws[IMX8MM_CLK_SAI5] = imx8m_clk_hw_composite("sai5", imx8mm_sai5_sels, base + 0xa780);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) hws[IMX8MM_CLK_SAI6] = imx8m_clk_hw_composite("sai6", imx8mm_sai6_sels, base + 0xa800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) hws[IMX8MM_CLK_SPDIF1] = imx8m_clk_hw_composite("spdif1", imx8mm_spdif1_sels, base + 0xa880);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) hws[IMX8MM_CLK_SPDIF2] = imx8m_clk_hw_composite("spdif2", imx8mm_spdif2_sels, base + 0xa900);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) hws[IMX8MM_CLK_ENET_REF] = imx8m_clk_hw_composite("enet_ref", imx8mm_enet_ref_sels, base + 0xa980);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) hws[IMX8MM_CLK_ENET_TIMER] = imx8m_clk_hw_composite("enet_timer", imx8mm_enet_timer_sels, base + 0xaa00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) hws[IMX8MM_CLK_ENET_PHY_REF] = imx8m_clk_hw_composite("enet_phy", imx8mm_enet_phy_sels, base + 0xaa80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) hws[IMX8MM_CLK_NAND] = imx8m_clk_hw_composite("nand", imx8mm_nand_sels, base + 0xab00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) hws[IMX8MM_CLK_QSPI] = imx8m_clk_hw_composite("qspi", imx8mm_qspi_sels, base + 0xab80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) hws[IMX8MM_CLK_USDHC1] = imx8m_clk_hw_composite("usdhc1", imx8mm_usdhc1_sels, base + 0xac00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) hws[IMX8MM_CLK_USDHC2] = imx8m_clk_hw_composite("usdhc2", imx8mm_usdhc2_sels, base + 0xac80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) hws[IMX8MM_CLK_I2C1] = imx8m_clk_hw_composite("i2c1", imx8mm_i2c1_sels, base + 0xad00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) hws[IMX8MM_CLK_I2C2] = imx8m_clk_hw_composite("i2c2", imx8mm_i2c2_sels, base + 0xad80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) hws[IMX8MM_CLK_I2C3] = imx8m_clk_hw_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) hws[IMX8MM_CLK_I2C4] = imx8m_clk_hw_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) hws[IMX8MM_CLK_UART1] = imx8m_clk_hw_composite("uart1", imx8mm_uart1_sels, base + 0xaf00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) hws[IMX8MM_CLK_UART2] = imx8m_clk_hw_composite("uart2", imx8mm_uart2_sels, base + 0xaf80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) hws[IMX8MM_CLK_UART3] = imx8m_clk_hw_composite("uart3", imx8mm_uart3_sels, base + 0xb000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) hws[IMX8MM_CLK_UART4] = imx8m_clk_hw_composite("uart4", imx8mm_uart4_sels, base + 0xb080);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) hws[IMX8MM_CLK_USB_CORE_REF] = imx8m_clk_hw_composite("usb_core_ref", imx8mm_usb_core_sels, base + 0xb100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) hws[IMX8MM_CLK_USB_PHY_REF] = imx8m_clk_hw_composite("usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) hws[IMX8MM_CLK_GIC] = imx8m_clk_hw_composite_critical("gic", imx8mm_gic_sels, base + 0xb200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) hws[IMX8MM_CLK_ECSPI1] = imx8m_clk_hw_composite("ecspi1", imx8mm_ecspi1_sels, base + 0xb280);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) hws[IMX8MM_CLK_ECSPI2] = imx8m_clk_hw_composite("ecspi2", imx8mm_ecspi2_sels, base + 0xb300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) hws[IMX8MM_CLK_PWM1] = imx8m_clk_hw_composite("pwm1", imx8mm_pwm1_sels, base + 0xb380);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) hws[IMX8MM_CLK_PWM2] = imx8m_clk_hw_composite("pwm2", imx8mm_pwm2_sels, base + 0xb400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) hws[IMX8MM_CLK_PWM3] = imx8m_clk_hw_composite("pwm3", imx8mm_pwm3_sels, base + 0xb480);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) hws[IMX8MM_CLK_PWM4] = imx8m_clk_hw_composite("pwm4", imx8mm_pwm4_sels, base + 0xb500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) hws[IMX8MM_CLK_GPT1] = imx8m_clk_hw_composite("gpt1", imx8mm_gpt1_sels, base + 0xb580);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) hws[IMX8MM_CLK_WDOG] = imx8m_clk_hw_composite("wdog", imx8mm_wdog_sels, base + 0xb900);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) hws[IMX8MM_CLK_WRCLK] = imx8m_clk_hw_composite("wrclk", imx8mm_wrclk_sels, base + 0xb980);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) hws[IMX8MM_CLK_CLKO1] = imx8m_clk_hw_composite("clko1", imx8mm_clko1_sels, base + 0xba00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) hws[IMX8MM_CLK_CLKO2] = imx8m_clk_hw_composite("clko2", imx8mm_clko2_sels, base + 0xba80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) hws[IMX8MM_CLK_DSI_CORE] = imx8m_clk_hw_composite("dsi_core", imx8mm_dsi_core_sels, base + 0xbb00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) hws[IMX8MM_CLK_DSI_PHY_REF] = imx8m_clk_hw_composite("dsi_phy_ref", imx8mm_dsi_phy_sels, base + 0xbb80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) hws[IMX8MM_CLK_DSI_DBI] = imx8m_clk_hw_composite("dsi_dbi", imx8mm_dsi_dbi_sels, base + 0xbc00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) hws[IMX8MM_CLK_USDHC3] = imx8m_clk_hw_composite("usdhc3", imx8mm_usdhc3_sels, base + 0xbc80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) hws[IMX8MM_CLK_CSI1_CORE] = imx8m_clk_hw_composite("csi1_core", imx8mm_csi1_core_sels, base + 0xbd00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) hws[IMX8MM_CLK_CSI1_PHY_REF] = imx8m_clk_hw_composite("csi1_phy_ref", imx8mm_csi1_phy_sels, base + 0xbd80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) hws[IMX8MM_CLK_CSI1_ESC] = imx8m_clk_hw_composite("csi1_esc", imx8mm_csi1_esc_sels, base + 0xbe00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) hws[IMX8MM_CLK_CSI2_CORE] = imx8m_clk_hw_composite("csi2_core", imx8mm_csi2_core_sels, base + 0xbe80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) hws[IMX8MM_CLK_CSI2_PHY_REF] = imx8m_clk_hw_composite("csi2_phy_ref", imx8mm_csi2_phy_sels, base + 0xbf00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) hws[IMX8MM_CLK_CSI2_ESC] = imx8m_clk_hw_composite("csi2_esc", imx8mm_csi2_esc_sels, base + 0xbf80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) hws[IMX8MM_CLK_PCIE2_CTRL] = imx8m_clk_hw_composite("pcie2_ctrl", imx8mm_pcie2_ctrl_sels, base + 0xc000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) hws[IMX8MM_CLK_PCIE2_PHY] = imx8m_clk_hw_composite("pcie2_phy", imx8mm_pcie2_phy_sels, base + 0xc080);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) hws[IMX8MM_CLK_PCIE2_AUX] = imx8m_clk_hw_composite("pcie2_aux", imx8mm_pcie2_aux_sels, base + 0xc100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) hws[IMX8MM_CLK_ECSPI3] = imx8m_clk_hw_composite("ecspi3", imx8mm_ecspi3_sels, base + 0xc180);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) hws[IMX8MM_CLK_PDM] = imx8m_clk_hw_composite("pdm", imx8mm_pdm_sels, base + 0xc200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) hws[IMX8MM_CLK_VPU_H1] = imx8m_clk_hw_composite("vpu_h1", imx8mm_vpu_h1_sels, base + 0xc280);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* CCGR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) hws[IMX8MM_CLK_ECSPI1_ROOT] = imx_clk_hw_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) hws[IMX8MM_CLK_ECSPI2_ROOT] = imx_clk_hw_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) hws[IMX8MM_CLK_ECSPI3_ROOT] = imx_clk_hw_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) hws[IMX8MM_CLK_ENET1_ROOT] = imx_clk_hw_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) hws[IMX8MM_CLK_GPIO1_ROOT] = imx_clk_hw_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) hws[IMX8MM_CLK_GPIO2_ROOT] = imx_clk_hw_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) hws[IMX8MM_CLK_GPIO3_ROOT] = imx_clk_hw_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) hws[IMX8MM_CLK_GPIO4_ROOT] = imx_clk_hw_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) hws[IMX8MM_CLK_GPIO5_ROOT] = imx_clk_hw_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) hws[IMX8MM_CLK_GPT1_ROOT] = imx_clk_hw_gate4("gpt1_root_clk", "gpt1", base + 0x4100, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) hws[IMX8MM_CLK_I2C1_ROOT] = imx_clk_hw_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) hws[IMX8MM_CLK_I2C2_ROOT] = imx_clk_hw_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) hws[IMX8MM_CLK_I2C3_ROOT] = imx_clk_hw_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) hws[IMX8MM_CLK_I2C4_ROOT] = imx_clk_hw_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) hws[IMX8MM_CLK_MU_ROOT] = imx_clk_hw_gate4("mu_root_clk", "ipg_root", base + 0x4210, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) hws[IMX8MM_CLK_OCOTP_ROOT] = imx_clk_hw_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) hws[IMX8MM_CLK_PCIE1_ROOT] = imx_clk_hw_gate4("pcie1_root_clk", "pcie1_ctrl", base + 0x4250, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) hws[IMX8MM_CLK_PWM1_ROOT] = imx_clk_hw_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) hws[IMX8MM_CLK_PWM2_ROOT] = imx_clk_hw_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) hws[IMX8MM_CLK_PWM3_ROOT] = imx_clk_hw_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) hws[IMX8MM_CLK_PWM4_ROOT] = imx_clk_hw_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) hws[IMX8MM_CLK_QSPI_ROOT] = imx_clk_hw_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) hws[IMX8MM_CLK_NAND_ROOT] = imx_clk_hw_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) hws[IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_hw_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus", base + 0x4300, 0, &share_count_nand);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) hws[IMX8MM_CLK_SAI1_ROOT] = imx_clk_hw_gate2_shared2("sai1_root_clk", "sai1", base + 0x4330, 0, &share_count_sai1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) hws[IMX8MM_CLK_SAI1_IPG] = imx_clk_hw_gate2_shared2("sai1_ipg_clk", "ipg_audio_root", base + 0x4330, 0, &share_count_sai1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) hws[IMX8MM_CLK_SAI2_ROOT] = imx_clk_hw_gate2_shared2("sai2_root_clk", "sai2", base + 0x4340, 0, &share_count_sai2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) hws[IMX8MM_CLK_SAI2_IPG] = imx_clk_hw_gate2_shared2("sai2_ipg_clk", "ipg_audio_root", base + 0x4340, 0, &share_count_sai2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) hws[IMX8MM_CLK_SAI3_ROOT] = imx_clk_hw_gate2_shared2("sai3_root_clk", "sai3", base + 0x4350, 0, &share_count_sai3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) hws[IMX8MM_CLK_SAI3_IPG] = imx_clk_hw_gate2_shared2("sai3_ipg_clk", "ipg_audio_root", base + 0x4350, 0, &share_count_sai3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) hws[IMX8MM_CLK_SAI4_ROOT] = imx_clk_hw_gate2_shared2("sai4_root_clk", "sai4", base + 0x4360, 0, &share_count_sai4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) hws[IMX8MM_CLK_SAI4_IPG] = imx_clk_hw_gate2_shared2("sai4_ipg_clk", "ipg_audio_root", base + 0x4360, 0, &share_count_sai4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) hws[IMX8MM_CLK_SAI5_ROOT] = imx_clk_hw_gate2_shared2("sai5_root_clk", "sai5", base + 0x4370, 0, &share_count_sai5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) hws[IMX8MM_CLK_SAI5_IPG] = imx_clk_hw_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) hws[IMX8MM_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) hws[IMX8MM_CLK_SAI6_IPG] = imx_clk_hw_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) hws[IMX8MM_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk", "ipg_root", base + 0x4470, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) hws[IMX8MM_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk", "uart1", base + 0x4490, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) hws[IMX8MM_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) hws[IMX8MM_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) hws[IMX8MM_CLK_UART4_ROOT] = imx_clk_hw_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) hws[IMX8MM_CLK_USB1_CTRL_ROOT] = imx_clk_hw_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) hws[IMX8MM_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk", "gpu3d_core", base + 0x44f0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) hws[IMX8MM_CLK_USDHC1_ROOT] = imx_clk_hw_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) hws[IMX8MM_CLK_USDHC2_ROOT] = imx_clk_hw_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) hws[IMX8MM_CLK_WDOG1_ROOT] = imx_clk_hw_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) hws[IMX8MM_CLK_WDOG2_ROOT] = imx_clk_hw_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) hws[IMX8MM_CLK_WDOG3_ROOT] = imx_clk_hw_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) hws[IMX8MM_CLK_VPU_G1_ROOT] = imx_clk_hw_gate4("vpu_g1_root_clk", "vpu_g1", base + 0x4560, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) hws[IMX8MM_CLK_GPU_BUS_ROOT] = imx_clk_hw_gate4("gpu_root_clk", "gpu_axi", base + 0x4570, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) hws[IMX8MM_CLK_VPU_H1_ROOT] = imx_clk_hw_gate4("vpu_h1_root_clk", "vpu_h1", base + 0x4590, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) hws[IMX8MM_CLK_VPU_G2_ROOT] = imx_clk_hw_gate4("vpu_g2_root_clk", "vpu_g2", base + 0x45a0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) hws[IMX8MM_CLK_PDM_ROOT] = imx_clk_hw_gate2_shared2("pdm_root_clk", "pdm", base + 0x45b0, 0, &share_count_pdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) hws[IMX8MM_CLK_PDM_IPG] = imx_clk_hw_gate2_shared2("pdm_ipg_clk", "ipg_audio_root", base + 0x45b0, 0, &share_count_pdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) hws[IMX8MM_CLK_DISP_ROOT] = imx_clk_hw_gate2_shared2("disp_root_clk", "disp_dc8000", base + 0x45d0, 0, &share_count_disp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) hws[IMX8MM_CLK_DISP_AXI_ROOT] = imx_clk_hw_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_disp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) hws[IMX8MM_CLK_DISP_APB_ROOT] = imx_clk_hw_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_disp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) hws[IMX8MM_CLK_DISP_RTRM_ROOT] = imx_clk_hw_gate2_shared2("disp_rtrm_root_clk", "disp_rtrm", base + 0x45d0, 0, &share_count_disp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) hws[IMX8MM_CLK_USDHC3_ROOT] = imx_clk_hw_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) hws[IMX8MM_CLK_TMU_ROOT] = imx_clk_hw_gate4("tmu_root_clk", "ipg_root", base + 0x4620, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) hws[IMX8MM_CLK_VPU_DEC_ROOT] = imx_clk_hw_gate4("vpu_dec_root_clk", "vpu_bus", base + 0x4630, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) hws[IMX8MM_CLK_SDMA1_ROOT] = imx_clk_hw_gate4("sdma1_clk", "ipg_root", base + 0x43a0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) hws[IMX8MM_CLK_SDMA2_ROOT] = imx_clk_hw_gate4("sdma2_clk", "ipg_audio_root", base + 0x43b0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) hws[IMX8MM_CLK_SDMA3_ROOT] = imx_clk_hw_gate4("sdma3_clk", "ipg_audio_root", base + 0x45f0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) hws[IMX8MM_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk", "gpu2d_core", base + 0x4660, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) hws[IMX8MM_CLK_CSI1_ROOT] = imx_clk_hw_gate4("csi1_root_clk", "csi1_core", base + 0x4650, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) hws[IMX8MM_CLK_GPT_3M] = imx_clk_hw_fixed_factor("gpt_3m", "osc_24m", 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) hws[IMX8MM_CLK_DRAM_ALT_ROOT] = imx_clk_hw_fixed_factor("dram_alt_root", "dram_alt", 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) hws[IMX8MM_CLK_DRAM_CORE] = imx_clk_hw_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mm_dram_core_sels, ARRAY_SIZE(imx8mm_dram_core_sels), CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) hws[IMX8MM_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) hws[IMX8MM_CLK_A53_CORE]->clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) hws[IMX8MM_CLK_A53_CORE]->clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) hws[IMX8MM_ARM_PLL_OUT]->clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) hws[IMX8MM_CLK_A53_DIV]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) imx_check_clk_hws(hws, IMX8MM_CLK_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) dev_err(dev, "failed to register clks for i.MX8MM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) goto unregister_hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) imx_register_uart_clocks(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) unregister_hws:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) imx_unregister_hw_clocks(hws, IMX8MM_CLK_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static const struct of_device_id imx8mm_clk_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) { .compatible = "fsl,imx8mm-ccm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) { /* Sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) MODULE_DEVICE_TABLE(of, imx8mm_clk_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static struct platform_driver imx8mm_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .probe = imx8mm_clocks_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .name = "imx8mm-ccm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * Disable bind attributes: clocks are not removed and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * reloading the driver will crash or break devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .of_match_table = of_match_ptr(imx8mm_clk_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) module_platform_driver(imx8mm_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) MODULE_AUTHOR("Bai Ping <ping.bai@nxp.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) MODULE_DESCRIPTION("NXP i.MX8MM clock driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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