Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <dt-bindings/clock/imx7d-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) static u32 share_count_sai1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) static u32 share_count_sai2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) static u32 share_count_sai3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) static u32 share_count_nand;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) static u32 share_count_enet1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static u32 share_count_enet2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static const struct clk_div_table test_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	{ .val = 3, .div = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	{ .val = 2, .div = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	{ .val = 1, .div = 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	{ .val = 0, .div = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static const struct clk_div_table post_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	{ .val = 3, .div = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	{ .val = 2, .div = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	{ .val = 1, .div = 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	{ .val = 0, .div = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static const char *arm_a7_sel[] = { "osc", "pll_arm_main_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	"pll_enet_500m_clk", "pll_dram_main_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	"pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_audio_post_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	"pll_usb_main_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static const char *arm_m4_sel[] = { "osc", "pll_sys_main_240m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	"pll_enet_250m_clk", "pll_sys_pfd2_270m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	"pll_dram_533m_clk", "pll_audio_post_div", "pll_video_post_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	"pll_usb_main_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static const char *axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	"pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd5_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	"pll_audio_post_div", "pll_video_post_div", "pll_sys_pfd7_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static const char *disp_axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	"pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd6_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	"pll_sys_pfd7_clk", "pll_audio_post_div", "pll_video_post_div", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static const char *enet_axi_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	"pll_dram_533m_clk", "pll_enet_250m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	"pll_sys_main_240m_clk", "pll_audio_post_div", "pll_video_post_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	"pll_sys_pfd4_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	"pll_dram_533m_clk", "pll_sys_main_240m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	"pll_sys_pfd2_135m_clk", "pll_sys_pfd6_clk", "pll_enet_250m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	"pll_audio_post_div", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	"pll_dram_533m_clk", "pll_sys_pfd0_392m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	"pll_enet_250m_clk", "pll_usb_main_clk", "pll_audio_post_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	"pll_video_post_div", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static const char *dram_phym_sel[] = { "pll_dram_main_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	"dram_phym_alt_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static const char *dram_sel[] = { "pll_dram_main_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	"dram_alt_root_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static const char *dram_phym_alt_sel[] = { "osc", "pll_dram_533m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	"pll_sys_main_clk", "pll_enet_500m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	"pll_usb_main_clk", "pll_sys_pfd7_clk", "pll_audio_post_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	"pll_video_post_div", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static const char *dram_alt_sel[] = { "osc", "pll_dram_533m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	"pll_sys_main_clk", "pll_enet_500m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	"pll_enet_250m_clk", "pll_sys_pfd0_392m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	"pll_audio_post_div", "pll_sys_pfd2_270m_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static const char *usb_hsic_sel[] = { "osc", "pll_sys_main_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	"pll_usb_main_clk", "pll_sys_pfd3_clk", "pll_sys_pfd4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	"pll_sys_pfd5_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static const char *pcie_ctrl_sel[] = { "osc", "pll_enet_250m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	"pll_sys_main_240m_clk", "pll_sys_pfd2_270m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	"pll_dram_533m_clk", "pll_enet_500m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	"pll_sys_pfd1_332m_clk", "pll_sys_pfd6_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const char *pcie_phy_sel[] = { "osc", "pll_enet_100m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	"pll_enet_500m_clk", "ext_clk_1", "ext_clk_2", "ext_clk_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	"ext_clk_4", "pll_sys_pfd0_392m_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static const char *epdc_pixel_sel[] = { "osc", "pll_sys_pfd1_332m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	"pll_dram_533m_clk", "pll_sys_main_clk", "pll_sys_pfd5_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	"pll_sys_pfd6_clk", "pll_sys_pfd7_clk", "pll_video_post_div", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static const char *lcdif_pixel_sel[] = { "osc", "pll_sys_pfd5_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	"pll_dram_533m_clk", "ext_clk_3", "pll_sys_pfd4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	"pll_sys_pfd2_270m_clk", "pll_video_post_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	"pll_usb_main_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const char *mipi_dsi_sel[] = { "osc", "pll_sys_pfd5_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	"pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	"pll_dram_533m_clk", "pll_video_post_div", "pll_audio_post_div", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const char *mipi_csi_sel[] = { "osc", "pll_sys_pfd4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	"pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	"pll_dram_533m_clk", "pll_video_post_div", "pll_audio_post_div", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const char *mipi_dphy_sel[] = { "osc", "pll_sys_main_120m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	"pll_dram_533m_clk", "pll_sys_pfd5_clk", "ref_1m_clk", "ext_clk_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	"pll_video_post_div", "ext_clk_3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const char *sai1_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	"pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const char *sai2_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	"pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const char *sai3_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	"pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static const char *spdif_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	"pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_3_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const char *enet1_ref_sel[] = { "osc", "pll_enet_125m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	"pll_enet_50m_clk", "pll_enet_25m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	"pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_post_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	"ext_clk_4", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const char *enet1_time_sel[] = { "osc", "pll_enet_100m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	"pll_audio_post_div", "ext_clk_1", "ext_clk_2", "ext_clk_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	"ext_clk_4", "pll_video_post_div", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const char *enet2_ref_sel[] = { "osc", "pll_enet_125m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	"pll_enet_50m_clk", "pll_enet_25m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	"pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_post_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	"ext_clk_4", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const char *enet2_time_sel[] = { "osc", "pll_enet_100m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	"pll_audio_post_div", "ext_clk_1", "ext_clk_2", "ext_clk_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	"ext_clk_4", "pll_video_post_div", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const char *enet_phy_ref_sel[] = { "osc", "pll_enet_25m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	"pll_enet_50m_clk", "pll_enet_125m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	"pll_dram_533m_clk", "pll_audio_post_div", "pll_video_post_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	"pll_sys_pfd3_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const char *eim_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	"pll_sys_main_120m_clk", "pll_dram_533m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	"pll_sys_pfd2_270m_clk", "pll_sys_pfd3_clk", "pll_enet_125m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	"pll_usb_main_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const char *nand_sel[] = { "osc", "pll_sys_main_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	"pll_dram_533m_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	"pll_enet_500m_clk", "pll_enet_250m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	"pll_video_post_div", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const char *qspi_sel[] = { "osc", "pll_sys_pfd4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	"pll_dram_533m_clk", "pll_enet_500m_clk", "pll_sys_pfd3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	"pll_sys_pfd2_270m_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const char *usdhc1_sel[] = { "osc", "pll_sys_pfd0_392m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	"pll_dram_533m_clk", "pll_enet_500m_clk", "pll_sys_pfd4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	"pll_sys_pfd2_270m_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const char *usdhc2_sel[] = { "osc", "pll_sys_pfd0_392m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	"pll_dram_533m_clk", "pll_enet_500m_clk", "pll_sys_pfd4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	"pll_sys_pfd2_270m_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static const char *usdhc3_sel[] = { "osc", "pll_sys_pfd0_392m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	"pll_dram_533m_clk", "pll_enet_500m_clk", "pll_sys_pfd4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	"pll_sys_pfd2_270m_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const char *can1_sel[] = { "osc", "pll_sys_main_120m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	"pll_dram_533m_clk", "pll_sys_main_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	"pll_enet_40m_clk", "pll_usb_main_clk", "ext_clk_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	"ext_clk_4", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static const char *can2_sel[] = { "osc", "pll_sys_main_120m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	"pll_dram_533m_clk", "pll_sys_main_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	"pll_enet_40m_clk", "pll_usb_main_clk", "ext_clk_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	"ext_clk_3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const char *i2c1_sel[] = { "osc", "pll_sys_main_120m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	"pll_enet_50m_clk", "pll_dram_533m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	"pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	"pll_sys_pfd2_135m_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const char *i2c2_sel[] = { "osc", "pll_sys_main_120m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	"pll_enet_50m_clk", "pll_dram_533m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	"pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	"pll_sys_pfd2_135m_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const char *i2c3_sel[] = { "osc", "pll_sys_main_120m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	"pll_enet_50m_clk", "pll_dram_533m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	"pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	"pll_sys_pfd2_135m_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static const char *i2c4_sel[] = { "osc", "pll_sys_main_120m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	"pll_enet_50m_clk", "pll_dram_533m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	"pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	"pll_sys_pfd2_135m_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const char *uart1_sel[] = { "osc", "pll_sys_main_240m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	"pll_enet_40m_clk", "pll_enet_100m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	"pll_sys_main_clk", "ext_clk_2", "ext_clk_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	"pll_usb_main_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const char *uart2_sel[] = { "osc", "pll_sys_main_240m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	"pll_enet_40m_clk", "pll_enet_100m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	"pll_sys_main_clk", "ext_clk_2", "ext_clk_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	"pll_usb_main_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const char *uart3_sel[] = { "osc", "pll_sys_main_240m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	"pll_enet_40m_clk", "pll_enet_100m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	"pll_sys_main_clk", "ext_clk_2", "ext_clk_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	"pll_usb_main_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const char *uart4_sel[] = { "osc", "pll_sys_main_240m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	"pll_enet_40m_clk", "pll_enet_100m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	"pll_sys_main_clk", "ext_clk_2", "ext_clk_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	"pll_usb_main_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const char *uart5_sel[] = { "osc", "pll_sys_main_240m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	"pll_enet_40m_clk", "pll_enet_100m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	"pll_sys_main_clk", "ext_clk_2", "ext_clk_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	"pll_usb_main_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const char *uart6_sel[] = { "osc", "pll_sys_main_240m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	"pll_enet_40m_clk", "pll_enet_100m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	"pll_sys_main_clk", "ext_clk_2", "ext_clk_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	"pll_usb_main_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const char *uart7_sel[] = { "osc", "pll_sys_main_240m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	"pll_enet_40m_clk", "pll_enet_100m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	"pll_sys_main_clk", "ext_clk_2", "ext_clk_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	"pll_usb_main_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static const char *ecspi1_sel[] = { "osc", "pll_sys_main_240m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	"pll_enet_40m_clk", "pll_sys_main_120m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	"pll_sys_main_clk", "pll_sys_pfd4_clk", "pll_enet_250m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	"pll_usb_main_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static const char *ecspi2_sel[] = { "osc", "pll_sys_main_240m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	"pll_enet_40m_clk", "pll_sys_main_120m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	"pll_sys_main_clk", "pll_sys_pfd4_clk", "pll_enet_250m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	"pll_usb_main_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static const char *ecspi3_sel[] = { "osc", "pll_sys_main_240m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	"pll_enet_40m_clk", "pll_sys_main_120m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	"pll_sys_main_clk", "pll_sys_pfd4_clk", "pll_enet_250m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	"pll_usb_main_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const char *ecspi4_sel[] = { "osc", "pll_sys_main_240m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	"pll_enet_40m_clk", "pll_sys_main_120m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	"pll_sys_main_clk", "pll_sys_pfd4_clk", "pll_enet_250m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	"pll_usb_main_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const char *pwm1_sel[] = { "osc", "pll_enet_100m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	"ext_clk_1", "ref_1m_clk", "pll_video_post_div", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static const char *pwm2_sel[] = { "osc", "pll_enet_100m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	"ext_clk_1", "ref_1m_clk", "pll_video_post_div", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const char *pwm3_sel[] = { "osc", "pll_enet_100m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	"ext_clk_2", "ref_1m_clk", "pll_video_post_div", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const char *pwm4_sel[] = { "osc", "pll_enet_100m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	"ext_clk_2", "ref_1m_clk", "pll_video_post_div", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static const char *flextimer1_sel[] = { "osc", "pll_enet_100m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	"ext_clk_3", "ref_1m_clk", "pll_video_post_div", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const char *flextimer2_sel[] = { "osc", "pll_enet_100m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	"ext_clk_3", "ref_1m_clk", "pll_video_post_div", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const char *sim1_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	"pll_sys_main_120m_clk", "pll_dram_533m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	"pll_usb_main_clk", "pll_audio_post_div", "pll_enet_125m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	"pll_sys_pfd7_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const char *sim2_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	"pll_sys_main_120m_clk", "pll_dram_533m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	"pll_usb_main_clk", "pll_video_post_div", "pll_enet_125m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	"pll_sys_pfd7_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static const char *gpt1_sel[] = { "osc", "pll_enet_100m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	"ref_1m_clk", "pll_audio_post_div", "ext_clk_1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static const char *gpt2_sel[] = { "osc", "pll_enet_100m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	"ref_1m_clk", "pll_audio_post_div", "ext_clk_2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const char *gpt3_sel[] = { "osc", "pll_enet_100m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	"ref_1m_clk", "pll_audio_post_div", "ext_clk_3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static const char *gpt4_sel[] = { "osc", "pll_enet_100m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	"ref_1m_clk", "pll_audio_post_div", "ext_clk_4", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static const char *trace_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	"pll_sys_main_120m_clk", "pll_dram_533m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	"pll_enet_125m_clk", "pll_usb_main_clk", "ext_clk_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	"ext_clk_3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const char *wdog_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	"pll_sys_main_120m_clk", "pll_dram_533m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	"pll_enet_125m_clk", "pll_usb_main_clk", "ref_1m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	"pll_sys_pfd1_166m_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const char *csi_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	"pll_sys_main_120m_clk", "pll_dram_533m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	"pll_enet_125m_clk", "pll_audio_post_div", "pll_video_post_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	"pll_usb_main_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static const char *audio_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	"pll_sys_main_120m_clk", "pll_dram_533m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	"pll_enet_125m_clk", "pll_audio_post_div", "pll_video_post_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	"pll_usb_main_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static const char *wrclk_sel[] = { "osc", "pll_enet_40m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	"pll_dram_533m_clk", "pll_usb_main_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	"pll_sys_main_240m_clk", "pll_sys_pfd2_270m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	"pll_enet_500m_clk", "pll_sys_pfd7_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static const char *clko1_sel[] = { "osc", "pll_sys_main_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	"pll_sys_main_240m_clk", "pll_sys_pfd0_196m_clk", "pll_sys_pfd3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	"pll_enet_500m_clk", "pll_dram_533m_clk", "ref_1m_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static const char *clko2_sel[] = { "osc", "pll_sys_main_240m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	"pll_sys_pfd0_392m_clk", "pll_sys_pfd1_166m_clk", "pll_sys_pfd4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	"pll_audio_post_div", "pll_video_post_div", "ckil", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const char *lvds1_sel[] = { "pll_arm_main_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	"pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_332m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	"pll_sys_pfd2_270m_clk", "pll_sys_pfd3_clk", "pll_sys_pfd4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	"pll_sys_pfd5_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	"pll_audio_post_div", "pll_video_post_div", "pll_enet_500m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	"pll_enet_250m_clk", "pll_enet_125m_clk", "pll_enet_100m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	"pll_enet_50m_clk", "pll_enet_40m_clk", "pll_enet_25m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	"pll_dram_main_clk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static const char *pll_bypass_src_sel[] = { "osc", "dummy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static const char *pll_arm_bypass_sel[] = { "pll_arm_main", "pll_arm_main_src", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static const char *pll_dram_bypass_sel[] = { "pll_dram_main", "pll_dram_main_src", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static const char *pll_sys_bypass_sel[] = { "pll_sys_main", "pll_sys_main_src", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const char *pll_enet_bypass_sel[] = { "pll_enet_main", "pll_enet_main_src", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static const char *pll_audio_bypass_sel[] = { "pll_audio_main", "pll_audio_main_src", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static const char *pll_video_bypass_sel[] = { "pll_video_main", "pll_video_main_src", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static struct clk_hw **hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static struct clk_hw_onecell_data *clk_hw_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static void __init imx7d_clocks_init(struct device_node *ccm_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 					  IMX7D_CLK_END), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	if (WARN_ON(!clk_hw_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	clk_hw_data->num = IMX7D_CLK_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	hws = clk_hw_data->hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	hws[IMX7D_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	hws[IMX7D_OSC_24M_CLK] = imx_obtain_fixed_clk_hw(ccm_node, "osc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	hws[IMX7D_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-anatop");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	WARN_ON(!base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	hws[IMX7D_PLL_ARM_MAIN_SRC]  = imx_clk_hw_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	hws[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_hw_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	hws[IMX7D_PLL_SYS_MAIN_SRC]  = imx_clk_hw_mux("pll_sys_main_src", base + 0xb0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	hws[IMX7D_PLL_ENET_MAIN_SRC] = imx_clk_hw_mux("pll_enet_main_src", base + 0xe0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	hws[IMX7D_PLL_AUDIO_MAIN_SRC] = imx_clk_hw_mux("pll_audio_main_src", base + 0xf0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	hws[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_hw_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	hws[IMX7D_PLL_ARM_MAIN]  = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll_arm_main", "osc", base + 0x60, 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	hws[IMX7D_PLL_DRAM_MAIN] = imx_clk_hw_pllv3(IMX_PLLV3_DDR_IMX7, "pll_dram_main", "osc", base + 0x70, 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	hws[IMX7D_PLL_SYS_MAIN]  = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll_sys_main", "osc", base + 0xb0, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	hws[IMX7D_PLL_ENET_MAIN] = imx_clk_hw_pllv3(IMX_PLLV3_ENET_IMX7, "pll_enet_main", "osc", base + 0xe0, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	hws[IMX7D_PLL_AUDIO_MAIN] = imx_clk_hw_pllv3(IMX_PLLV3_AV_IMX7, "pll_audio_main", "osc", base + 0xf0, 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	hws[IMX7D_PLL_VIDEO_MAIN] = imx_clk_hw_pllv3(IMX_PLLV3_AV_IMX7, "pll_video_main", "osc", base + 0x130, 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	hws[IMX7D_PLL_ARM_MAIN_BYPASS]  = imx_clk_hw_mux_flags("pll_arm_main_bypass", base + 0x60, 16, 1, pll_arm_bypass_sel, ARRAY_SIZE(pll_arm_bypass_sel), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	hws[IMX7D_PLL_DRAM_MAIN_BYPASS] = imx_clk_hw_mux_flags("pll_dram_main_bypass", base + 0x70, 16, 1, pll_dram_bypass_sel, ARRAY_SIZE(pll_dram_bypass_sel), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	hws[IMX7D_PLL_SYS_MAIN_BYPASS]  = imx_clk_hw_mux_flags("pll_sys_main_bypass", base + 0xb0, 16, 1, pll_sys_bypass_sel, ARRAY_SIZE(pll_sys_bypass_sel), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	hws[IMX7D_PLL_ENET_MAIN_BYPASS] = imx_clk_hw_mux_flags("pll_enet_main_bypass", base + 0xe0, 16, 1, pll_enet_bypass_sel, ARRAY_SIZE(pll_enet_bypass_sel), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	hws[IMX7D_PLL_AUDIO_MAIN_BYPASS] = imx_clk_hw_mux_flags("pll_audio_main_bypass", base + 0xf0, 16, 1, pll_audio_bypass_sel, ARRAY_SIZE(pll_audio_bypass_sel), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	hws[IMX7D_PLL_VIDEO_MAIN_BYPASS] = imx_clk_hw_mux_flags("pll_video_main_bypass", base + 0x130, 16, 1, pll_video_bypass_sel, ARRAY_SIZE(pll_video_bypass_sel), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	hws[IMX7D_PLL_ARM_MAIN_CLK] = imx_clk_hw_gate("pll_arm_main_clk", "pll_arm_main_bypass", base + 0x60, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	hws[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_hw_gate("pll_dram_main_clk", "pll_dram_test_div", base + 0x70, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	hws[IMX7D_PLL_SYS_MAIN_CLK] = imx_clk_hw_gate("pll_sys_main_clk", "pll_sys_main_bypass", base + 0xb0, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	hws[IMX7D_PLL_AUDIO_MAIN_CLK] = imx_clk_hw_gate("pll_audio_main_clk", "pll_audio_main_bypass", base + 0xf0, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	hws[IMX7D_PLL_VIDEO_MAIN_CLK] = imx_clk_hw_gate("pll_video_main_clk", "pll_video_main_bypass", base + 0x130, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	hws[IMX7D_PLL_DRAM_TEST_DIV]  = clk_hw_register_divider_table(NULL, "pll_dram_test_div", "pll_dram_main_bypass",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 				CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 21, 2, 0, test_div_table, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	hws[IMX7D_PLL_AUDIO_TEST_DIV]  = clk_hw_register_divider_table(NULL, "pll_audio_test_div", "pll_audio_main_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 				CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 19, 2, 0, test_div_table, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	hws[IMX7D_PLL_AUDIO_POST_DIV] = clk_hw_register_divider_table(NULL, "pll_audio_post_div", "pll_audio_test_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 				CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 22, 2, 0, post_div_table, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	hws[IMX7D_PLL_VIDEO_TEST_DIV]  = clk_hw_register_divider_table(NULL, "pll_video_test_div", "pll_video_main_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 				CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x130, 19, 2, 0, test_div_table, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	hws[IMX7D_PLL_VIDEO_POST_DIV] = clk_hw_register_divider_table(NULL, "pll_video_post_div", "pll_video_test_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 				CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x130, 22, 2, 0, post_div_table, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	hws[IMX7D_PLL_SYS_PFD0_392M_CLK] = imx_clk_hw_pfd("pll_sys_pfd0_392m_clk", "pll_sys_main_clk", base + 0xc0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	hws[IMX7D_PLL_SYS_PFD1_332M_CLK] = imx_clk_hw_pfd("pll_sys_pfd1_332m_clk", "pll_sys_main_clk", base + 0xc0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	hws[IMX7D_PLL_SYS_PFD2_270M_CLK] = imx_clk_hw_pfd("pll_sys_pfd2_270m_clk", "pll_sys_main_clk", base + 0xc0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	hws[IMX7D_PLL_SYS_PFD3_CLK] = imx_clk_hw_pfd("pll_sys_pfd3_clk", "pll_sys_main_clk", base + 0xc0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	hws[IMX7D_PLL_SYS_PFD4_CLK] = imx_clk_hw_pfd("pll_sys_pfd4_clk", "pll_sys_main_clk", base + 0xd0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	hws[IMX7D_PLL_SYS_PFD5_CLK] = imx_clk_hw_pfd("pll_sys_pfd5_clk", "pll_sys_main_clk", base + 0xd0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	hws[IMX7D_PLL_SYS_PFD6_CLK] = imx_clk_hw_pfd("pll_sys_pfd6_clk", "pll_sys_main_clk", base + 0xd0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	hws[IMX7D_PLL_SYS_PFD7_CLK] = imx_clk_hw_pfd("pll_sys_pfd7_clk", "pll_sys_main_clk", base + 0xd0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	hws[IMX7D_PLL_SYS_MAIN_480M] = imx_clk_hw_fixed_factor("pll_sys_main_480m", "pll_sys_main_clk", 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	hws[IMX7D_PLL_SYS_MAIN_240M] = imx_clk_hw_fixed_factor("pll_sys_main_240m", "pll_sys_main_clk", 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	hws[IMX7D_PLL_SYS_MAIN_120M] = imx_clk_hw_fixed_factor("pll_sys_main_120m", "pll_sys_main_clk", 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	hws[IMX7D_PLL_DRAM_MAIN_533M] = imx_clk_hw_fixed_factor("pll_dram_533m", "pll_dram_main_clk", 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	hws[IMX7D_PLL_SYS_MAIN_480M_CLK] = imx_clk_hw_gate_dis_flags("pll_sys_main_480m_clk", "pll_sys_main_480m", base + 0xb0, 4, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	hws[IMX7D_PLL_SYS_MAIN_240M_CLK] = imx_clk_hw_gate_dis("pll_sys_main_240m_clk", "pll_sys_main_240m", base + 0xb0, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	hws[IMX7D_PLL_SYS_MAIN_120M_CLK] = imx_clk_hw_gate_dis("pll_sys_main_120m_clk", "pll_sys_main_120m", base + 0xb0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	hws[IMX7D_PLL_DRAM_MAIN_533M_CLK] = imx_clk_hw_gate("pll_dram_533m_clk", "pll_dram_533m", base + 0x70, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	hws[IMX7D_PLL_SYS_PFD0_196M] = imx_clk_hw_fixed_factor("pll_sys_pfd0_196m", "pll_sys_pfd0_392m_clk", 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	hws[IMX7D_PLL_SYS_PFD1_166M] = imx_clk_hw_fixed_factor("pll_sys_pfd1_166m", "pll_sys_pfd1_332m_clk", 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	hws[IMX7D_PLL_SYS_PFD2_135M] = imx_clk_hw_fixed_factor("pll_sys_pfd2_135m", "pll_sys_pfd2_270m_clk", 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	hws[IMX7D_PLL_SYS_PFD0_196M_CLK] = imx_clk_hw_gate_dis("pll_sys_pfd0_196m_clk", "pll_sys_pfd0_196m", base + 0xb0, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	hws[IMX7D_PLL_SYS_PFD1_166M_CLK] = imx_clk_hw_gate_dis("pll_sys_pfd1_166m_clk", "pll_sys_pfd1_166m", base + 0xb0, 27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	hws[IMX7D_PLL_SYS_PFD2_135M_CLK] = imx_clk_hw_gate_dis("pll_sys_pfd2_135m_clk", "pll_sys_pfd2_135m", base + 0xb0, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	hws[IMX7D_PLL_ENET_MAIN_CLK] = imx_clk_hw_fixed_factor("pll_enet_main_clk", "pll_enet_main_bypass", 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	hws[IMX7D_PLL_ENET_MAIN_500M] = imx_clk_hw_fixed_factor("pll_enet_500m", "pll_enet_main_clk", 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	hws[IMX7D_PLL_ENET_MAIN_250M] = imx_clk_hw_fixed_factor("pll_enet_250m", "pll_enet_main_clk", 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	hws[IMX7D_PLL_ENET_MAIN_125M] = imx_clk_hw_fixed_factor("pll_enet_125m", "pll_enet_main_clk", 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	hws[IMX7D_PLL_ENET_MAIN_100M] = imx_clk_hw_fixed_factor("pll_enet_100m", "pll_enet_main_clk", 1, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	hws[IMX7D_PLL_ENET_MAIN_50M] = imx_clk_hw_fixed_factor("pll_enet_50m", "pll_enet_main_clk", 1, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	hws[IMX7D_PLL_ENET_MAIN_40M] = imx_clk_hw_fixed_factor("pll_enet_40m", "pll_enet_main_clk", 1, 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	hws[IMX7D_PLL_ENET_MAIN_25M] = imx_clk_hw_fixed_factor("pll_enet_25m", "pll_enet_main_clk", 1, 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	hws[IMX7D_PLL_ENET_MAIN_500M_CLK] = imx_clk_hw_gate("pll_enet_500m_clk", "pll_enet_500m", base + 0xe0, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	hws[IMX7D_PLL_ENET_MAIN_250M_CLK] = imx_clk_hw_gate("pll_enet_250m_clk", "pll_enet_250m", base + 0xe0, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	hws[IMX7D_PLL_ENET_MAIN_125M_CLK] = imx_clk_hw_gate("pll_enet_125m_clk", "pll_enet_125m", base + 0xe0, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	hws[IMX7D_PLL_ENET_MAIN_100M_CLK] = imx_clk_hw_gate("pll_enet_100m_clk", "pll_enet_100m", base + 0xe0, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	hws[IMX7D_PLL_ENET_MAIN_50M_CLK]  = imx_clk_hw_gate("pll_enet_50m_clk", "pll_enet_50m", base + 0xe0, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	hws[IMX7D_PLL_ENET_MAIN_40M_CLK]  = imx_clk_hw_gate("pll_enet_40m_clk", "pll_enet_40m", base + 0xe0, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	hws[IMX7D_PLL_ENET_MAIN_25M_CLK]  = imx_clk_hw_gate("pll_enet_25m_clk", "pll_enet_25m", base + 0xe0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	hws[IMX7D_LVDS1_OUT_SEL] = imx_clk_hw_mux("lvds1_sel", base + 0x170, 0, 5, lvds1_sel, ARRAY_SIZE(lvds1_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	hws[IMX7D_LVDS1_OUT_CLK] = imx_clk_hw_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x170, 5, BIT(6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	np = ccm_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	WARN_ON(!base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	hws[IMX7D_ARM_A7_ROOT_SRC] = imx_clk_hw_mux2("arm_a7_src", base + 0x8000, 24, 3, arm_a7_sel, ARRAY_SIZE(arm_a7_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	hws[IMX7D_ARM_M4_ROOT_SRC] = imx_clk_hw_mux2("arm_m4_src", base + 0x8080, 24, 3, arm_m4_sel, ARRAY_SIZE(arm_m4_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	hws[IMX7D_MAIN_AXI_ROOT_SRC] = imx_clk_hw_mux2("axi_src", base + 0x8800, 24, 3, axi_sel, ARRAY_SIZE(axi_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	hws[IMX7D_DISP_AXI_ROOT_SRC] = imx_clk_hw_mux2("disp_axi_src", base + 0x8880, 24, 3, disp_axi_sel, ARRAY_SIZE(disp_axi_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	hws[IMX7D_AHB_CHANNEL_ROOT_SRC] = imx_clk_hw_mux2("ahb_src", base + 0x9000, 24, 3, ahb_channel_sel, ARRAY_SIZE(ahb_channel_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	hws[IMX7D_ENET_AXI_ROOT_SRC] = imx_clk_hw_mux2_flags("enet_axi_src", base + 0x8900, 24, 3, enet_axi_sel, ARRAY_SIZE(enet_axi_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	hws[IMX7D_NAND_USDHC_BUS_ROOT_SRC] = imx_clk_hw_mux2_flags("nand_usdhc_src", base + 0x8980, 24, 3, nand_usdhc_bus_sel, ARRAY_SIZE(nand_usdhc_bus_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	hws[IMX7D_DRAM_PHYM_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_phym_src", base + 0x9800, 24, 1, dram_phym_sel, ARRAY_SIZE(dram_phym_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	hws[IMX7D_DRAM_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_src", base + 0x9880, 24, 1, dram_sel, ARRAY_SIZE(dram_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	hws[IMX7D_DRAM_PHYM_ALT_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_phym_alt_src", base + 0xa000, 24, 3, dram_phym_alt_sel, ARRAY_SIZE(dram_phym_alt_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	hws[IMX7D_DRAM_ALT_ROOT_SRC]  = imx_clk_hw_mux2_flags("dram_alt_src", base + 0xa080, 24, 3, dram_alt_sel, ARRAY_SIZE(dram_alt_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	hws[IMX7D_USB_HSIC_ROOT_SRC] = imx_clk_hw_mux2_flags("usb_hsic_src", base + 0xa100, 24, 3, usb_hsic_sel, ARRAY_SIZE(usb_hsic_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	hws[IMX7D_PCIE_CTRL_ROOT_SRC] = imx_clk_hw_mux2_flags("pcie_ctrl_src", base + 0xa180, 24, 3, pcie_ctrl_sel, ARRAY_SIZE(pcie_ctrl_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	hws[IMX7D_PCIE_PHY_ROOT_SRC] = imx_clk_hw_mux2_flags("pcie_phy_src", base + 0xa200, 24, 3, pcie_phy_sel, ARRAY_SIZE(pcie_phy_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	hws[IMX7D_EPDC_PIXEL_ROOT_SRC] = imx_clk_hw_mux2_flags("epdc_pixel_src", base + 0xa280, 24, 3, epdc_pixel_sel, ARRAY_SIZE(epdc_pixel_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	hws[IMX7D_LCDIF_PIXEL_ROOT_SRC] = imx_clk_hw_mux2_flags("lcdif_pixel_src", base + 0xa300, 24, 3, lcdif_pixel_sel, ARRAY_SIZE(lcdif_pixel_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	hws[IMX7D_MIPI_DSI_ROOT_SRC] = imx_clk_hw_mux2_flags("mipi_dsi_src", base + 0xa380, 24, 3,  mipi_dsi_sel, ARRAY_SIZE(mipi_dsi_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	hws[IMX7D_MIPI_CSI_ROOT_SRC] = imx_clk_hw_mux2_flags("mipi_csi_src", base + 0xa400, 24, 3, mipi_csi_sel, ARRAY_SIZE(mipi_csi_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	hws[IMX7D_MIPI_DPHY_ROOT_SRC] = imx_clk_hw_mux2_flags("mipi_dphy_src", base + 0xa480, 24, 3, mipi_dphy_sel, ARRAY_SIZE(mipi_dphy_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	hws[IMX7D_SAI1_ROOT_SRC] = imx_clk_hw_mux2_flags("sai1_src", base + 0xa500, 24, 3, sai1_sel, ARRAY_SIZE(sai1_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	hws[IMX7D_SAI2_ROOT_SRC] = imx_clk_hw_mux2_flags("sai2_src", base + 0xa580, 24, 3, sai2_sel, ARRAY_SIZE(sai2_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	hws[IMX7D_SAI3_ROOT_SRC] = imx_clk_hw_mux2_flags("sai3_src", base + 0xa600, 24, 3, sai3_sel, ARRAY_SIZE(sai3_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	hws[IMX7D_SPDIF_ROOT_SRC] = imx_clk_hw_mux2_flags("spdif_src", base + 0xa680, 24, 3, spdif_sel, ARRAY_SIZE(spdif_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	hws[IMX7D_ENET1_REF_ROOT_SRC] = imx_clk_hw_mux2_flags("enet1_ref_src", base + 0xa700, 24, 3, enet1_ref_sel, ARRAY_SIZE(enet1_ref_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	hws[IMX7D_ENET1_TIME_ROOT_SRC] = imx_clk_hw_mux2_flags("enet1_time_src", base + 0xa780, 24, 3, enet1_time_sel, ARRAY_SIZE(enet1_time_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	hws[IMX7D_ENET2_REF_ROOT_SRC] = imx_clk_hw_mux2_flags("enet2_ref_src", base + 0xa800, 24, 3, enet2_ref_sel, ARRAY_SIZE(enet2_ref_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	hws[IMX7D_ENET2_TIME_ROOT_SRC] = imx_clk_hw_mux2_flags("enet2_time_src", base + 0xa880, 24, 3, enet2_time_sel, ARRAY_SIZE(enet2_time_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	hws[IMX7D_ENET_PHY_REF_ROOT_SRC] = imx_clk_hw_mux2_flags("enet_phy_ref_src", base + 0xa900, 24, 3, enet_phy_ref_sel, ARRAY_SIZE(enet_phy_ref_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	hws[IMX7D_EIM_ROOT_SRC] = imx_clk_hw_mux2_flags("eim_src", base + 0xa980, 24, 3, eim_sel, ARRAY_SIZE(eim_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	hws[IMX7D_NAND_ROOT_SRC] = imx_clk_hw_mux2_flags("nand_src", base + 0xaa00, 24, 3, nand_sel, ARRAY_SIZE(nand_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	hws[IMX7D_QSPI_ROOT_SRC] = imx_clk_hw_mux2_flags("qspi_src", base + 0xaa80, 24, 3, qspi_sel, ARRAY_SIZE(qspi_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	hws[IMX7D_USDHC1_ROOT_SRC] = imx_clk_hw_mux2_flags("usdhc1_src", base + 0xab00, 24, 3, usdhc1_sel, ARRAY_SIZE(usdhc1_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	hws[IMX7D_USDHC2_ROOT_SRC] = imx_clk_hw_mux2_flags("usdhc2_src", base + 0xab80, 24, 3, usdhc2_sel, ARRAY_SIZE(usdhc2_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	hws[IMX7D_USDHC3_ROOT_SRC] = imx_clk_hw_mux2_flags("usdhc3_src", base + 0xac00, 24, 3, usdhc3_sel, ARRAY_SIZE(usdhc3_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	hws[IMX7D_CAN1_ROOT_SRC] = imx_clk_hw_mux2_flags("can1_src", base + 0xac80, 24, 3, can1_sel, ARRAY_SIZE(can1_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	hws[IMX7D_CAN2_ROOT_SRC] = imx_clk_hw_mux2_flags("can2_src", base + 0xad00, 24, 3, can2_sel, ARRAY_SIZE(can2_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	hws[IMX7D_I2C1_ROOT_SRC] = imx_clk_hw_mux2_flags("i2c1_src", base + 0xad80, 24, 3, i2c1_sel, ARRAY_SIZE(i2c1_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	hws[IMX7D_I2C2_ROOT_SRC] = imx_clk_hw_mux2_flags("i2c2_src", base + 0xae00, 24, 3, i2c2_sel, ARRAY_SIZE(i2c2_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	hws[IMX7D_I2C3_ROOT_SRC] = imx_clk_hw_mux2_flags("i2c3_src", base + 0xae80, 24, 3, i2c3_sel, ARRAY_SIZE(i2c3_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	hws[IMX7D_I2C4_ROOT_SRC] = imx_clk_hw_mux2_flags("i2c4_src", base + 0xaf00, 24, 3, i2c4_sel, ARRAY_SIZE(i2c4_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	hws[IMX7D_UART1_ROOT_SRC] = imx_clk_hw_mux2_flags("uart1_src", base + 0xaf80, 24, 3, uart1_sel, ARRAY_SIZE(uart1_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	hws[IMX7D_UART2_ROOT_SRC] = imx_clk_hw_mux2_flags("uart2_src", base + 0xb000, 24, 3, uart2_sel, ARRAY_SIZE(uart2_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	hws[IMX7D_UART3_ROOT_SRC] = imx_clk_hw_mux2_flags("uart3_src", base + 0xb080, 24, 3, uart3_sel, ARRAY_SIZE(uart3_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	hws[IMX7D_UART4_ROOT_SRC] = imx_clk_hw_mux2_flags("uart4_src", base + 0xb100, 24, 3, uart4_sel, ARRAY_SIZE(uart4_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	hws[IMX7D_UART5_ROOT_SRC] = imx_clk_hw_mux2_flags("uart5_src", base + 0xb180, 24, 3, uart5_sel, ARRAY_SIZE(uart5_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	hws[IMX7D_UART6_ROOT_SRC] = imx_clk_hw_mux2_flags("uart6_src", base + 0xb200, 24, 3, uart6_sel, ARRAY_SIZE(uart6_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	hws[IMX7D_UART7_ROOT_SRC] = imx_clk_hw_mux2_flags("uart7_src", base + 0xb280, 24, 3, uart7_sel, ARRAY_SIZE(uart7_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	hws[IMX7D_ECSPI1_ROOT_SRC] = imx_clk_hw_mux2_flags("ecspi1_src", base + 0xb300, 24, 3, ecspi1_sel, ARRAY_SIZE(ecspi1_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	hws[IMX7D_ECSPI2_ROOT_SRC] = imx_clk_hw_mux2_flags("ecspi2_src", base + 0xb380, 24, 3, ecspi2_sel, ARRAY_SIZE(ecspi2_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	hws[IMX7D_ECSPI3_ROOT_SRC] = imx_clk_hw_mux2_flags("ecspi3_src", base + 0xb400, 24, 3, ecspi3_sel, ARRAY_SIZE(ecspi3_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	hws[IMX7D_ECSPI4_ROOT_SRC] = imx_clk_hw_mux2_flags("ecspi4_src", base + 0xb480, 24, 3, ecspi4_sel, ARRAY_SIZE(ecspi4_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 	hws[IMX7D_PWM1_ROOT_SRC] = imx_clk_hw_mux2_flags("pwm1_src", base + 0xb500, 24, 3, pwm1_sel, ARRAY_SIZE(pwm1_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	hws[IMX7D_PWM2_ROOT_SRC] = imx_clk_hw_mux2_flags("pwm2_src", base + 0xb580, 24, 3, pwm2_sel, ARRAY_SIZE(pwm2_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	hws[IMX7D_PWM3_ROOT_SRC] = imx_clk_hw_mux2_flags("pwm3_src", base + 0xb600, 24, 3, pwm3_sel, ARRAY_SIZE(pwm3_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	hws[IMX7D_PWM4_ROOT_SRC] = imx_clk_hw_mux2_flags("pwm4_src", base + 0xb680, 24, 3, pwm4_sel, ARRAY_SIZE(pwm4_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	hws[IMX7D_FLEXTIMER1_ROOT_SRC] = imx_clk_hw_mux2_flags("flextimer1_src", base + 0xb700, 24, 3, flextimer1_sel, ARRAY_SIZE(flextimer1_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 	hws[IMX7D_FLEXTIMER2_ROOT_SRC] = imx_clk_hw_mux2_flags("flextimer2_src", base + 0xb780, 24, 3, flextimer2_sel, ARRAY_SIZE(flextimer2_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	hws[IMX7D_SIM1_ROOT_SRC] = imx_clk_hw_mux2_flags("sim1_src", base + 0xb800, 24, 3, sim1_sel, ARRAY_SIZE(sim1_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	hws[IMX7D_SIM2_ROOT_SRC] = imx_clk_hw_mux2_flags("sim2_src", base + 0xb880, 24, 3, sim2_sel, ARRAY_SIZE(sim2_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	hws[IMX7D_GPT1_ROOT_SRC] = imx_clk_hw_mux2_flags("gpt1_src", base + 0xb900, 24, 3, gpt1_sel, ARRAY_SIZE(gpt1_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	hws[IMX7D_GPT2_ROOT_SRC] = imx_clk_hw_mux2_flags("gpt2_src", base + 0xb980, 24, 3, gpt2_sel, ARRAY_SIZE(gpt2_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	hws[IMX7D_GPT3_ROOT_SRC] = imx_clk_hw_mux2_flags("gpt3_src", base + 0xba00, 24, 3, gpt3_sel, ARRAY_SIZE(gpt3_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	hws[IMX7D_GPT4_ROOT_SRC] = imx_clk_hw_mux2_flags("gpt4_src", base + 0xba80, 24, 3, gpt4_sel, ARRAY_SIZE(gpt4_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	hws[IMX7D_TRACE_ROOT_SRC] = imx_clk_hw_mux2_flags("trace_src", base + 0xbb00, 24, 3, trace_sel, ARRAY_SIZE(trace_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 	hws[IMX7D_WDOG_ROOT_SRC] = imx_clk_hw_mux2_flags("wdog_src", base + 0xbb80, 24, 3, wdog_sel, ARRAY_SIZE(wdog_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	hws[IMX7D_CSI_MCLK_ROOT_SRC] = imx_clk_hw_mux2_flags("csi_mclk_src", base + 0xbc00, 24, 3, csi_mclk_sel, ARRAY_SIZE(csi_mclk_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 	hws[IMX7D_AUDIO_MCLK_ROOT_SRC] = imx_clk_hw_mux2_flags("audio_mclk_src", base + 0xbc80, 24, 3, audio_mclk_sel, ARRAY_SIZE(audio_mclk_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 	hws[IMX7D_WRCLK_ROOT_SRC] = imx_clk_hw_mux2_flags("wrclk_src", base + 0xbd00, 24, 3, wrclk_sel, ARRAY_SIZE(wrclk_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	hws[IMX7D_CLKO1_ROOT_SRC] = imx_clk_hw_mux2_flags("clko1_src", base + 0xbd80, 24, 3, clko1_sel, ARRAY_SIZE(clko1_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	hws[IMX7D_CLKO2_ROOT_SRC] = imx_clk_hw_mux2_flags("clko2_src", base + 0xbe00, 24, 3, clko2_sel, ARRAY_SIZE(clko2_sel), CLK_SET_PARENT_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 	hws[IMX7D_ARM_A7_ROOT_CG] = imx_clk_hw_gate3("arm_a7_cg", "arm_a7_src", base + 0x8000, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 	hws[IMX7D_ARM_M4_ROOT_CG] = imx_clk_hw_gate3("arm_m4_cg", "arm_m4_src", base + 0x8080, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	hws[IMX7D_MAIN_AXI_ROOT_CG] = imx_clk_hw_gate3("axi_cg", "axi_src", base + 0x8800, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 	hws[IMX7D_DISP_AXI_ROOT_CG] = imx_clk_hw_gate3("disp_axi_cg", "disp_axi_src", base + 0x8880, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 	hws[IMX7D_ENET_AXI_ROOT_CG] = imx_clk_hw_gate3("enet_axi_cg", "enet_axi_src", base + 0x8900, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 	hws[IMX7D_NAND_USDHC_BUS_ROOT_CG] = imx_clk_hw_gate3("nand_usdhc_cg", "nand_usdhc_src", base + 0x8980, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 	hws[IMX7D_AHB_CHANNEL_ROOT_CG] = imx_clk_hw_gate3("ahb_cg", "ahb_src", base + 0x9000, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 	hws[IMX7D_DRAM_PHYM_ROOT_CG] = imx_clk_hw_gate3("dram_phym_cg", "dram_phym_src", base + 0x9800, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 	hws[IMX7D_DRAM_ROOT_CG] = imx_clk_hw_gate3("dram_cg", "dram_src", base + 0x9880, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 	hws[IMX7D_DRAM_PHYM_ALT_ROOT_CG] = imx_clk_hw_gate3("dram_phym_alt_cg", "dram_phym_alt_src", base + 0xa000, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 	hws[IMX7D_DRAM_ALT_ROOT_CG] = imx_clk_hw_gate3("dram_alt_cg", "dram_alt_src", base + 0xa080, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 	hws[IMX7D_USB_HSIC_ROOT_CG] = imx_clk_hw_gate3("usb_hsic_cg", "usb_hsic_src", base + 0xa100, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 	hws[IMX7D_PCIE_CTRL_ROOT_CG] = imx_clk_hw_gate3("pcie_ctrl_cg", "pcie_ctrl_src", base + 0xa180, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 	hws[IMX7D_PCIE_PHY_ROOT_CG] = imx_clk_hw_gate3("pcie_phy_cg", "pcie_phy_src", base + 0xa200, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	hws[IMX7D_EPDC_PIXEL_ROOT_CG] = imx_clk_hw_gate3("epdc_pixel_cg", "epdc_pixel_src", base + 0xa280, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 	hws[IMX7D_LCDIF_PIXEL_ROOT_CG] = imx_clk_hw_gate3("lcdif_pixel_cg", "lcdif_pixel_src", base + 0xa300, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 	hws[IMX7D_MIPI_DSI_ROOT_CG] = imx_clk_hw_gate3("mipi_dsi_cg", "mipi_dsi_src", base + 0xa380, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 	hws[IMX7D_MIPI_CSI_ROOT_CG] = imx_clk_hw_gate3("mipi_csi_cg", "mipi_csi_src", base + 0xa400, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 	hws[IMX7D_MIPI_DPHY_ROOT_CG] = imx_clk_hw_gate3("mipi_dphy_cg", "mipi_dphy_src", base + 0xa480, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 	hws[IMX7D_SAI1_ROOT_CG] = imx_clk_hw_gate3("sai1_cg", "sai1_src", base + 0xa500, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 	hws[IMX7D_SAI2_ROOT_CG] = imx_clk_hw_gate3("sai2_cg", "sai2_src", base + 0xa580, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 	hws[IMX7D_SAI3_ROOT_CG] = imx_clk_hw_gate3("sai3_cg", "sai3_src", base + 0xa600, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	hws[IMX7D_SPDIF_ROOT_CG] = imx_clk_hw_gate3("spdif_cg", "spdif_src", base + 0xa680, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 	hws[IMX7D_ENET1_REF_ROOT_CG] = imx_clk_hw_gate3("enet1_ref_cg", "enet1_ref_src", base + 0xa700, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 	hws[IMX7D_ENET1_TIME_ROOT_CG] = imx_clk_hw_gate3("enet1_time_cg", "enet1_time_src", base + 0xa780, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 	hws[IMX7D_ENET2_REF_ROOT_CG] = imx_clk_hw_gate3("enet2_ref_cg", "enet2_ref_src", base + 0xa800, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 	hws[IMX7D_ENET2_TIME_ROOT_CG] = imx_clk_hw_gate3("enet2_time_cg", "enet2_time_src", base + 0xa880, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 	hws[IMX7D_ENET_PHY_REF_ROOT_CG] = imx_clk_hw_gate3("enet_phy_ref_cg", "enet_phy_ref_src", base + 0xa900, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 	hws[IMX7D_EIM_ROOT_CG] = imx_clk_hw_gate3("eim_cg", "eim_src", base + 0xa980, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 	hws[IMX7D_NAND_ROOT_CG] = imx_clk_hw_gate3("nand_cg", "nand_src", base + 0xaa00, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 	hws[IMX7D_QSPI_ROOT_CG] = imx_clk_hw_gate3("qspi_cg", "qspi_src", base + 0xaa80, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 	hws[IMX7D_USDHC1_ROOT_CG] = imx_clk_hw_gate3("usdhc1_cg", "usdhc1_src", base + 0xab00, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 	hws[IMX7D_USDHC2_ROOT_CG] = imx_clk_hw_gate3("usdhc2_cg", "usdhc2_src", base + 0xab80, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 	hws[IMX7D_USDHC3_ROOT_CG] = imx_clk_hw_gate3("usdhc3_cg", "usdhc3_src", base + 0xac00, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 	hws[IMX7D_CAN1_ROOT_CG] = imx_clk_hw_gate3("can1_cg", "can1_src", base + 0xac80, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 	hws[IMX7D_CAN2_ROOT_CG] = imx_clk_hw_gate3("can2_cg", "can2_src", base + 0xad00, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 	hws[IMX7D_I2C1_ROOT_CG] = imx_clk_hw_gate3("i2c1_cg", "i2c1_src", base + 0xad80, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 	hws[IMX7D_I2C2_ROOT_CG] = imx_clk_hw_gate3("i2c2_cg", "i2c2_src", base + 0xae00, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 	hws[IMX7D_I2C3_ROOT_CG] = imx_clk_hw_gate3("i2c3_cg", "i2c3_src", base + 0xae80, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 	hws[IMX7D_I2C4_ROOT_CG] = imx_clk_hw_gate3("i2c4_cg", "i2c4_src", base + 0xaf00, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 	hws[IMX7D_UART1_ROOT_CG] = imx_clk_hw_gate3("uart1_cg", "uart1_src", base + 0xaf80, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 	hws[IMX7D_UART2_ROOT_CG] = imx_clk_hw_gate3("uart2_cg", "uart2_src", base + 0xb000, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 	hws[IMX7D_UART3_ROOT_CG] = imx_clk_hw_gate3("uart3_cg", "uart3_src", base + 0xb080, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 	hws[IMX7D_UART4_ROOT_CG] = imx_clk_hw_gate3("uart4_cg", "uart4_src", base + 0xb100, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 	hws[IMX7D_UART5_ROOT_CG] = imx_clk_hw_gate3("uart5_cg", "uart5_src", base + 0xb180, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 	hws[IMX7D_UART6_ROOT_CG] = imx_clk_hw_gate3("uart6_cg", "uart6_src", base + 0xb200, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 	hws[IMX7D_UART7_ROOT_CG] = imx_clk_hw_gate3("uart7_cg", "uart7_src", base + 0xb280, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 	hws[IMX7D_ECSPI1_ROOT_CG] = imx_clk_hw_gate3("ecspi1_cg", "ecspi1_src", base + 0xb300, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 	hws[IMX7D_ECSPI2_ROOT_CG] = imx_clk_hw_gate3("ecspi2_cg", "ecspi2_src", base + 0xb380, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 	hws[IMX7D_ECSPI3_ROOT_CG] = imx_clk_hw_gate3("ecspi3_cg", "ecspi3_src", base + 0xb400, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 	hws[IMX7D_ECSPI4_ROOT_CG] = imx_clk_hw_gate3("ecspi4_cg", "ecspi4_src", base + 0xb480, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 	hws[IMX7D_PWM1_ROOT_CG] = imx_clk_hw_gate3("pwm1_cg", "pwm1_src", base + 0xb500, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 	hws[IMX7D_PWM2_ROOT_CG] = imx_clk_hw_gate3("pwm2_cg", "pwm2_src", base + 0xb580, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 	hws[IMX7D_PWM3_ROOT_CG] = imx_clk_hw_gate3("pwm3_cg", "pwm3_src", base + 0xb600, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 	hws[IMX7D_PWM4_ROOT_CG] = imx_clk_hw_gate3("pwm4_cg", "pwm4_src", base + 0xb680, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 	hws[IMX7D_FLEXTIMER1_ROOT_CG] = imx_clk_hw_gate3("flextimer1_cg", "flextimer1_src", base + 0xb700, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 	hws[IMX7D_FLEXTIMER2_ROOT_CG] = imx_clk_hw_gate3("flextimer2_cg", "flextimer2_src", base + 0xb780, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 	hws[IMX7D_SIM1_ROOT_CG] = imx_clk_hw_gate3("sim1_cg", "sim1_src", base + 0xb800, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 	hws[IMX7D_SIM2_ROOT_CG] = imx_clk_hw_gate3("sim2_cg", "sim2_src", base + 0xb880, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 	hws[IMX7D_GPT1_ROOT_CG] = imx_clk_hw_gate3("gpt1_cg", "gpt1_src", base + 0xb900, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 	hws[IMX7D_GPT2_ROOT_CG] = imx_clk_hw_gate3("gpt2_cg", "gpt2_src", base + 0xb980, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 	hws[IMX7D_GPT3_ROOT_CG] = imx_clk_hw_gate3("gpt3_cg", "gpt3_src", base + 0xbA00, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 	hws[IMX7D_GPT4_ROOT_CG] = imx_clk_hw_gate3("gpt4_cg", "gpt4_src", base + 0xbA80, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 	hws[IMX7D_TRACE_ROOT_CG] = imx_clk_hw_gate3("trace_cg", "trace_src", base + 0xbb00, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 	hws[IMX7D_WDOG_ROOT_CG] = imx_clk_hw_gate3("wdog_cg", "wdog_src", base + 0xbb80, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 	hws[IMX7D_CSI_MCLK_ROOT_CG] = imx_clk_hw_gate3("csi_mclk_cg", "csi_mclk_src", base + 0xbc00, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 	hws[IMX7D_AUDIO_MCLK_ROOT_CG] = imx_clk_hw_gate3("audio_mclk_cg", "audio_mclk_src", base + 0xbc80, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 	hws[IMX7D_WRCLK_ROOT_CG] = imx_clk_hw_gate3("wrclk_cg", "wrclk_src", base + 0xbd00, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 	hws[IMX7D_CLKO1_ROOT_CG] = imx_clk_hw_gate3("clko1_cg", "clko1_src", base + 0xbd80, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 	hws[IMX7D_CLKO2_ROOT_CG] = imx_clk_hw_gate3("clko2_cg", "clko2_src", base + 0xbe00, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 	hws[IMX7D_MAIN_AXI_ROOT_PRE_DIV] = imx_clk_hw_divider2("axi_pre_div", "axi_cg", base + 0x8800, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 	hws[IMX7D_DISP_AXI_ROOT_PRE_DIV] = imx_clk_hw_divider2("disp_axi_pre_div", "disp_axi_cg", base + 0x8880, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 	hws[IMX7D_ENET_AXI_ROOT_PRE_DIV] = imx_clk_hw_divider2("enet_axi_pre_div", "enet_axi_cg", base + 0x8900, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 	hws[IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV] = imx_clk_hw_divider2("nand_usdhc_pre_div", "nand_usdhc_cg", base + 0x8980, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 	hws[IMX7D_AHB_CHANNEL_ROOT_PRE_DIV] = imx_clk_hw_divider2("ahb_pre_div", "ahb_cg", base + 0x9000, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 	hws[IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV] = imx_clk_hw_divider2("dram_phym_alt_pre_div", "dram_phym_alt_cg", base + 0xa000, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 	hws[IMX7D_DRAM_ALT_ROOT_PRE_DIV] = imx_clk_hw_divider2("dram_alt_pre_div", "dram_alt_cg", base + 0xa080, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 	hws[IMX7D_USB_HSIC_ROOT_PRE_DIV] = imx_clk_hw_divider2("usb_hsic_pre_div", "usb_hsic_cg", base + 0xa100, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 	hws[IMX7D_PCIE_CTRL_ROOT_PRE_DIV] = imx_clk_hw_divider2("pcie_ctrl_pre_div", "pcie_ctrl_cg", base + 0xa180, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 	hws[IMX7D_PCIE_PHY_ROOT_PRE_DIV] = imx_clk_hw_divider2("pcie_phy_pre_div", "pcie_phy_cg", base + 0xa200, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 	hws[IMX7D_EPDC_PIXEL_ROOT_PRE_DIV] = imx_clk_hw_divider2("epdc_pixel_pre_div", "epdc_pixel_cg", base + 0xa280, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 	hws[IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV] = imx_clk_hw_divider2("lcdif_pixel_pre_div", "lcdif_pixel_cg", base + 0xa300, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 	hws[IMX7D_MIPI_DSI_ROOT_PRE_DIV] = imx_clk_hw_divider2("mipi_dsi_pre_div", "mipi_dsi_cg", base + 0xa380, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 	hws[IMX7D_MIPI_CSI_ROOT_PRE_DIV] = imx_clk_hw_divider2("mipi_csi_pre_div", "mipi_csi_cg", base + 0xa400, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 	hws[IMX7D_MIPI_DPHY_ROOT_PRE_DIV] = imx_clk_hw_divider2("mipi_dphy_pre_div", "mipi_dphy_cg", base + 0xa480, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 	hws[IMX7D_SAI1_ROOT_PRE_DIV] = imx_clk_hw_divider2("sai1_pre_div", "sai1_cg", base + 0xa500, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 	hws[IMX7D_SAI2_ROOT_PRE_DIV] = imx_clk_hw_divider2("sai2_pre_div", "sai2_cg", base + 0xa580, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 	hws[IMX7D_SAI3_ROOT_PRE_DIV] = imx_clk_hw_divider2("sai3_pre_div", "sai3_cg", base + 0xa600, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 	hws[IMX7D_SPDIF_ROOT_PRE_DIV] = imx_clk_hw_divider2("spdif_pre_div", "spdif_cg", base + 0xa680, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 	hws[IMX7D_ENET1_REF_ROOT_PRE_DIV] = imx_clk_hw_divider2("enet1_ref_pre_div", "enet1_ref_cg", base + 0xa700, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 	hws[IMX7D_ENET1_TIME_ROOT_PRE_DIV] = imx_clk_hw_divider2("enet1_time_pre_div", "enet1_time_cg", base + 0xa780, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 	hws[IMX7D_ENET2_REF_ROOT_PRE_DIV] = imx_clk_hw_divider2("enet2_ref_pre_div", "enet2_ref_cg", base + 0xa800, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 	hws[IMX7D_ENET2_TIME_ROOT_PRE_DIV] = imx_clk_hw_divider2("enet2_time_pre_div", "enet2_time_cg", base + 0xa880, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 	hws[IMX7D_ENET_PHY_REF_ROOT_PRE_DIV] = imx_clk_hw_divider2("enet_phy_ref_pre_div", "enet_phy_ref_cg", base + 0xa900, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 	hws[IMX7D_EIM_ROOT_PRE_DIV] = imx_clk_hw_divider2("eim_pre_div", "eim_cg", base + 0xa980, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 	hws[IMX7D_NAND_ROOT_PRE_DIV] = imx_clk_hw_divider2("nand_pre_div", "nand_cg", base + 0xaa00, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 	hws[IMX7D_QSPI_ROOT_PRE_DIV] = imx_clk_hw_divider2("qspi_pre_div", "qspi_cg", base + 0xaa80, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) 	hws[IMX7D_USDHC1_ROOT_PRE_DIV] = imx_clk_hw_divider2("usdhc1_pre_div", "usdhc1_cg", base + 0xab00, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 	hws[IMX7D_USDHC2_ROOT_PRE_DIV] = imx_clk_hw_divider2("usdhc2_pre_div", "usdhc2_cg", base + 0xab80, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) 	hws[IMX7D_USDHC3_ROOT_PRE_DIV] = imx_clk_hw_divider2("usdhc3_pre_div", "usdhc3_cg", base + 0xac00, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 	hws[IMX7D_CAN1_ROOT_PRE_DIV] = imx_clk_hw_divider2("can1_pre_div", "can1_cg", base + 0xac80, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 	hws[IMX7D_CAN2_ROOT_PRE_DIV] = imx_clk_hw_divider2("can2_pre_div", "can2_cg", base + 0xad00, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) 	hws[IMX7D_I2C1_ROOT_PRE_DIV] = imx_clk_hw_divider2("i2c1_pre_div", "i2c1_cg", base + 0xad80, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 	hws[IMX7D_I2C2_ROOT_PRE_DIV] = imx_clk_hw_divider2("i2c2_pre_div", "i2c2_cg", base + 0xae00, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 	hws[IMX7D_I2C3_ROOT_PRE_DIV] = imx_clk_hw_divider2("i2c3_pre_div", "i2c3_cg", base + 0xae80, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 	hws[IMX7D_I2C4_ROOT_PRE_DIV] = imx_clk_hw_divider2("i2c4_pre_div", "i2c4_cg", base + 0xaf00, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 	hws[IMX7D_UART1_ROOT_PRE_DIV] = imx_clk_hw_divider2("uart1_pre_div", "uart1_cg", base + 0xaf80, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 	hws[IMX7D_UART2_ROOT_PRE_DIV] = imx_clk_hw_divider2("uart2_pre_div", "uart2_cg", base + 0xb000, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) 	hws[IMX7D_UART3_ROOT_PRE_DIV] = imx_clk_hw_divider2("uart3_pre_div", "uart3_cg", base + 0xb080, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) 	hws[IMX7D_UART4_ROOT_PRE_DIV] = imx_clk_hw_divider2("uart4_pre_div", "uart4_cg", base + 0xb100, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) 	hws[IMX7D_UART5_ROOT_PRE_DIV] = imx_clk_hw_divider2("uart5_pre_div", "uart5_cg", base + 0xb180, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) 	hws[IMX7D_UART6_ROOT_PRE_DIV] = imx_clk_hw_divider2("uart6_pre_div", "uart6_cg", base + 0xb200, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) 	hws[IMX7D_UART7_ROOT_PRE_DIV] = imx_clk_hw_divider2("uart7_pre_div", "uart7_cg", base + 0xb280, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) 	hws[IMX7D_ECSPI1_ROOT_PRE_DIV] = imx_clk_hw_divider2("ecspi1_pre_div", "ecspi1_cg", base + 0xb300, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 	hws[IMX7D_ECSPI2_ROOT_PRE_DIV] = imx_clk_hw_divider2("ecspi2_pre_div", "ecspi2_cg", base + 0xb380, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 	hws[IMX7D_ECSPI3_ROOT_PRE_DIV] = imx_clk_hw_divider2("ecspi3_pre_div", "ecspi3_cg", base + 0xb400, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) 	hws[IMX7D_ECSPI4_ROOT_PRE_DIV] = imx_clk_hw_divider2("ecspi4_pre_div", "ecspi4_cg", base + 0xb480, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) 	hws[IMX7D_PWM1_ROOT_PRE_DIV] = imx_clk_hw_divider2("pwm1_pre_div", "pwm1_cg", base + 0xb500, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) 	hws[IMX7D_PWM2_ROOT_PRE_DIV] = imx_clk_hw_divider2("pwm2_pre_div", "pwm2_cg", base + 0xb580, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) 	hws[IMX7D_PWM3_ROOT_PRE_DIV] = imx_clk_hw_divider2("pwm3_pre_div", "pwm3_cg", base + 0xb600, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) 	hws[IMX7D_PWM4_ROOT_PRE_DIV] = imx_clk_hw_divider2("pwm4_pre_div", "pwm4_cg", base + 0xb680, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) 	hws[IMX7D_FLEXTIMER1_ROOT_PRE_DIV] = imx_clk_hw_divider2("flextimer1_pre_div", "flextimer1_cg", base + 0xb700, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 	hws[IMX7D_FLEXTIMER2_ROOT_PRE_DIV] = imx_clk_hw_divider2("flextimer2_pre_div", "flextimer2_cg", base + 0xb780, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) 	hws[IMX7D_SIM1_ROOT_PRE_DIV] = imx_clk_hw_divider2("sim1_pre_div", "sim1_cg", base + 0xb800, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) 	hws[IMX7D_SIM2_ROOT_PRE_DIV] = imx_clk_hw_divider2("sim2_pre_div", "sim2_cg", base + 0xb880, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) 	hws[IMX7D_GPT1_ROOT_PRE_DIV] = imx_clk_hw_divider2("gpt1_pre_div", "gpt1_cg", base + 0xb900, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) 	hws[IMX7D_GPT2_ROOT_PRE_DIV] = imx_clk_hw_divider2("gpt2_pre_div", "gpt2_cg", base + 0xb980, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) 	hws[IMX7D_GPT3_ROOT_PRE_DIV] = imx_clk_hw_divider2("gpt3_pre_div", "gpt3_cg", base + 0xba00, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) 	hws[IMX7D_GPT4_ROOT_PRE_DIV] = imx_clk_hw_divider2("gpt4_pre_div", "gpt4_cg", base + 0xba80, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) 	hws[IMX7D_TRACE_ROOT_PRE_DIV] = imx_clk_hw_divider2("trace_pre_div", "trace_cg", base + 0xbb00, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) 	hws[IMX7D_WDOG_ROOT_PRE_DIV] = imx_clk_hw_divider2("wdog_pre_div", "wdog_cg", base + 0xbb80, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) 	hws[IMX7D_CSI_MCLK_ROOT_PRE_DIV] = imx_clk_hw_divider2("csi_mclk_pre_div", "csi_mclk_cg", base + 0xbc00, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) 	hws[IMX7D_AUDIO_MCLK_ROOT_PRE_DIV] = imx_clk_hw_divider2("audio_mclk_pre_div", "audio_mclk_cg", base + 0xbc80, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) 	hws[IMX7D_WRCLK_ROOT_PRE_DIV] = imx_clk_hw_divider2("wrclk_pre_div", "wrclk_cg", base + 0xbd00, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) 	hws[IMX7D_CLKO1_ROOT_PRE_DIV] = imx_clk_hw_divider2("clko1_pre_div", "clko1_cg", base + 0xbd80, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) 	hws[IMX7D_CLKO2_ROOT_PRE_DIV] = imx_clk_hw_divider2("clko2_pre_div", "clko2_cg", base + 0xbe00, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) 	hws[IMX7D_ARM_A7_ROOT_DIV] = imx_clk_hw_divider2("arm_a7_div", "arm_a7_cg", base + 0x8000, 0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 	hws[IMX7D_ARM_M4_ROOT_DIV] = imx_clk_hw_divider2("arm_m4_div", "arm_m4_cg", base + 0x8080, 0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) 	hws[IMX7D_MAIN_AXI_ROOT_DIV] = imx_clk_hw_divider2("axi_post_div", "axi_pre_div", base + 0x8800, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) 	hws[IMX7D_DISP_AXI_ROOT_DIV] = imx_clk_hw_divider2("disp_axi_post_div", "disp_axi_pre_div", base + 0x8880, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 	hws[IMX7D_ENET_AXI_ROOT_DIV] = imx_clk_hw_divider2("enet_axi_post_div", "enet_axi_pre_div", base + 0x8900, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) 	hws[IMX7D_NAND_USDHC_BUS_ROOT_CLK] = imx_clk_hw_divider2("nand_usdhc_root_clk", "nand_usdhc_pre_div", base + 0x8980, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) 	hws[IMX7D_AHB_CHANNEL_ROOT_DIV] = imx_clk_hw_divider2("ahb_root_clk", "ahb_pre_div", base + 0x9000, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) 	hws[IMX7D_IPG_ROOT_CLK] = imx_clk_hw_divider_flags("ipg_root_clk", "ahb_root_clk", base + 0x9080, 0, 2, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) 	hws[IMX7D_DRAM_ROOT_DIV] = imx_clk_hw_divider2("dram_post_div", "dram_cg", base + 0x9880, 0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) 	hws[IMX7D_DRAM_PHYM_ALT_ROOT_DIV] = imx_clk_hw_divider2("dram_phym_alt_post_div", "dram_phym_alt_pre_div", base + 0xa000, 0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) 	hws[IMX7D_DRAM_ALT_ROOT_DIV] = imx_clk_hw_divider2("dram_alt_post_div", "dram_alt_pre_div", base + 0xa080, 0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) 	hws[IMX7D_USB_HSIC_ROOT_DIV] = imx_clk_hw_divider2("usb_hsic_post_div", "usb_hsic_pre_div", base + 0xa100, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) 	hws[IMX7D_PCIE_CTRL_ROOT_DIV] = imx_clk_hw_divider2("pcie_ctrl_post_div", "pcie_ctrl_pre_div", base + 0xa180, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) 	hws[IMX7D_PCIE_PHY_ROOT_DIV] = imx_clk_hw_divider2("pcie_phy_post_div", "pcie_phy_pre_div", base + 0xa200, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) 	hws[IMX7D_EPDC_PIXEL_ROOT_DIV] = imx_clk_hw_divider2("epdc_pixel_post_div", "epdc_pixel_pre_div", base + 0xa280, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) 	hws[IMX7D_LCDIF_PIXEL_ROOT_DIV] = imx_clk_hw_divider2("lcdif_pixel_post_div", "lcdif_pixel_pre_div", base + 0xa300, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) 	hws[IMX7D_MIPI_DSI_ROOT_DIV] = imx_clk_hw_divider2("mipi_dsi_post_div", "mipi_dsi_pre_div", base + 0xa380, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) 	hws[IMX7D_MIPI_CSI_ROOT_DIV] = imx_clk_hw_divider2("mipi_csi_post_div", "mipi_csi_pre_div", base + 0xa400, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) 	hws[IMX7D_MIPI_DPHY_ROOT_DIV] = imx_clk_hw_divider2("mipi_dphy_post_div", "mipi_dphy_pre_div", base + 0xa480, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) 	hws[IMX7D_SAI1_ROOT_DIV] = imx_clk_hw_divider2("sai1_post_div", "sai1_pre_div", base + 0xa500, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) 	hws[IMX7D_SAI2_ROOT_DIV] = imx_clk_hw_divider2("sai2_post_div", "sai2_pre_div", base + 0xa580, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) 	hws[IMX7D_SAI3_ROOT_DIV] = imx_clk_hw_divider2("sai3_post_div", "sai3_pre_div", base + 0xa600, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) 	hws[IMX7D_SPDIF_ROOT_DIV] = imx_clk_hw_divider2("spdif_post_div", "spdif_pre_div", base + 0xa680, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) 	hws[IMX7D_ENET1_REF_ROOT_DIV] = imx_clk_hw_divider2("enet1_ref_post_div", "enet1_ref_pre_div", base + 0xa700, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) 	hws[IMX7D_ENET1_TIME_ROOT_DIV] = imx_clk_hw_divider2("enet1_time_post_div", "enet1_time_pre_div", base + 0xa780, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) 	hws[IMX7D_ENET2_REF_ROOT_DIV] = imx_clk_hw_divider2("enet2_ref_post_div", "enet2_ref_pre_div", base + 0xa800, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) 	hws[IMX7D_ENET2_TIME_ROOT_DIV] = imx_clk_hw_divider2("enet2_time_post_div", "enet2_time_pre_div", base + 0xa880, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) 	hws[IMX7D_ENET_PHY_REF_ROOT_CLK] = imx_clk_hw_divider2("enet_phy_ref_root_clk", "enet_phy_ref_pre_div", base + 0xa900, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) 	hws[IMX7D_EIM_ROOT_DIV] = imx_clk_hw_divider2("eim_post_div", "eim_pre_div", base + 0xa980, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) 	hws[IMX7D_NAND_ROOT_CLK] = imx_clk_hw_divider2("nand_root_clk", "nand_pre_div", base + 0xaa00, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) 	hws[IMX7D_QSPI_ROOT_DIV] = imx_clk_hw_divider2("qspi_post_div", "qspi_pre_div", base + 0xaa80, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) 	hws[IMX7D_USDHC1_ROOT_DIV] = imx_clk_hw_divider2("usdhc1_post_div", "usdhc1_pre_div", base + 0xab00, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) 	hws[IMX7D_USDHC2_ROOT_DIV] = imx_clk_hw_divider2("usdhc2_post_div", "usdhc2_pre_div", base + 0xab80, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) 	hws[IMX7D_USDHC3_ROOT_DIV] = imx_clk_hw_divider2("usdhc3_post_div", "usdhc3_pre_div", base + 0xac00, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) 	hws[IMX7D_CAN1_ROOT_DIV] = imx_clk_hw_divider2("can1_post_div", "can1_pre_div", base + 0xac80, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) 	hws[IMX7D_CAN2_ROOT_DIV] = imx_clk_hw_divider2("can2_post_div", "can2_pre_div", base + 0xad00, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) 	hws[IMX7D_I2C1_ROOT_DIV] = imx_clk_hw_divider2("i2c1_post_div", "i2c1_pre_div", base + 0xad80, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 	hws[IMX7D_I2C2_ROOT_DIV] = imx_clk_hw_divider2("i2c2_post_div", "i2c2_pre_div", base + 0xae00, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) 	hws[IMX7D_I2C3_ROOT_DIV] = imx_clk_hw_divider2("i2c3_post_div", "i2c3_pre_div", base + 0xae80, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) 	hws[IMX7D_I2C4_ROOT_DIV] = imx_clk_hw_divider2("i2c4_post_div", "i2c4_pre_div", base + 0xaf00, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) 	hws[IMX7D_UART1_ROOT_DIV] = imx_clk_hw_divider2("uart1_post_div", "uart1_pre_div", base + 0xaf80, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) 	hws[IMX7D_UART2_ROOT_DIV] = imx_clk_hw_divider2("uart2_post_div", "uart2_pre_div", base + 0xb000, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) 	hws[IMX7D_UART3_ROOT_DIV] = imx_clk_hw_divider2("uart3_post_div", "uart3_pre_div", base + 0xb080, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) 	hws[IMX7D_UART4_ROOT_DIV] = imx_clk_hw_divider2("uart4_post_div", "uart4_pre_div", base + 0xb100, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) 	hws[IMX7D_UART5_ROOT_DIV] = imx_clk_hw_divider2("uart5_post_div", "uart5_pre_div", base + 0xb180, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) 	hws[IMX7D_UART6_ROOT_DIV] = imx_clk_hw_divider2("uart6_post_div", "uart6_pre_div", base + 0xb200, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) 	hws[IMX7D_UART7_ROOT_DIV] = imx_clk_hw_divider2("uart7_post_div", "uart7_pre_div", base + 0xb280, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) 	hws[IMX7D_ECSPI1_ROOT_DIV] = imx_clk_hw_divider2("ecspi1_post_div", "ecspi1_pre_div", base + 0xb300, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) 	hws[IMX7D_ECSPI2_ROOT_DIV] = imx_clk_hw_divider2("ecspi2_post_div", "ecspi2_pre_div", base + 0xb380, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) 	hws[IMX7D_ECSPI3_ROOT_DIV] = imx_clk_hw_divider2("ecspi3_post_div", "ecspi3_pre_div", base + 0xb400, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) 	hws[IMX7D_ECSPI4_ROOT_DIV] = imx_clk_hw_divider2("ecspi4_post_div", "ecspi4_pre_div", base + 0xb480, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) 	hws[IMX7D_PWM1_ROOT_DIV] = imx_clk_hw_divider2("pwm1_post_div", "pwm1_pre_div", base + 0xb500, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) 	hws[IMX7D_PWM2_ROOT_DIV] = imx_clk_hw_divider2("pwm2_post_div", "pwm2_pre_div", base + 0xb580, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) 	hws[IMX7D_PWM3_ROOT_DIV] = imx_clk_hw_divider2("pwm3_post_div", "pwm3_pre_div", base + 0xb600, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) 	hws[IMX7D_PWM4_ROOT_DIV] = imx_clk_hw_divider2("pwm4_post_div", "pwm4_pre_div", base + 0xb680, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) 	hws[IMX7D_FLEXTIMER1_ROOT_DIV] = imx_clk_hw_divider2("flextimer1_post_div", "flextimer1_pre_div", base + 0xb700, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) 	hws[IMX7D_FLEXTIMER2_ROOT_DIV] = imx_clk_hw_divider2("flextimer2_post_div", "flextimer2_pre_div", base + 0xb780, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) 	hws[IMX7D_SIM1_ROOT_DIV] = imx_clk_hw_divider2("sim1_post_div", "sim1_pre_div", base + 0xb800, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) 	hws[IMX7D_SIM2_ROOT_DIV] = imx_clk_hw_divider2("sim2_post_div", "sim2_pre_div", base + 0xb880, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) 	hws[IMX7D_GPT1_ROOT_DIV] = imx_clk_hw_divider2("gpt1_post_div", "gpt1_pre_div", base + 0xb900, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) 	hws[IMX7D_GPT2_ROOT_DIV] = imx_clk_hw_divider2("gpt2_post_div", "gpt2_pre_div", base + 0xb980, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) 	hws[IMX7D_GPT3_ROOT_DIV] = imx_clk_hw_divider2("gpt3_post_div", "gpt3_pre_div", base + 0xba00, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) 	hws[IMX7D_GPT4_ROOT_DIV] = imx_clk_hw_divider2("gpt4_post_div", "gpt4_pre_div", base + 0xba80, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) 	hws[IMX7D_TRACE_ROOT_DIV] = imx_clk_hw_divider2("trace_post_div", "trace_pre_div", base + 0xbb00, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) 	hws[IMX7D_WDOG_ROOT_DIV] = imx_clk_hw_divider2("wdog_post_div", "wdog_pre_div", base + 0xbb80, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) 	hws[IMX7D_CSI_MCLK_ROOT_DIV] = imx_clk_hw_divider2("csi_mclk_post_div", "csi_mclk_pre_div", base + 0xbc00, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) 	hws[IMX7D_AUDIO_MCLK_ROOT_DIV] = imx_clk_hw_divider2("audio_mclk_post_div", "audio_mclk_pre_div", base + 0xbc80, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) 	hws[IMX7D_WRCLK_ROOT_DIV] = imx_clk_hw_divider2("wrclk_post_div", "wrclk_pre_div", base + 0xbd00, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) 	hws[IMX7D_CLKO1_ROOT_DIV] = imx_clk_hw_divider2("clko1_post_div", "clko1_pre_div", base + 0xbd80, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) 	hws[IMX7D_CLKO2_ROOT_DIV] = imx_clk_hw_divider2("clko2_post_div", "clko2_pre_div", base + 0xbe00, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) 	hws[IMX7D_ARM_A7_ROOT_CLK] = imx_clk_hw_gate2_flags("arm_a7_root_clk", "arm_a7_div", base + 0x4000, 0, CLK_OPS_PARENT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) 	hws[IMX7D_ARM_M4_ROOT_CLK] = imx_clk_hw_gate4("arm_m4_root_clk", "arm_m4_div", base + 0x4010, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) 	hws[IMX7D_MAIN_AXI_ROOT_CLK] = imx_clk_hw_gate2_flags("main_axi_root_clk", "axi_post_div", base + 0x4040, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) 	hws[IMX7D_DISP_AXI_ROOT_CLK] = imx_clk_hw_gate4("disp_axi_root_clk", "disp_axi_post_div", base + 0x4050, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) 	hws[IMX7D_ENET_AXI_ROOT_CLK] = imx_clk_hw_gate4("enet_axi_root_clk", "enet_axi_post_div", base + 0x4060, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) 	hws[IMX7D_OCRAM_CLK] = imx_clk_hw_gate4("ocram_clk", "main_axi_root_clk", base + 0x4110, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) 	hws[IMX7D_OCRAM_S_CLK] = imx_clk_hw_gate4("ocram_s_clk", "ahb_root_clk", base + 0x4120, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) 	hws[IMX7D_DRAM_ROOT_CLK] = imx_clk_hw_gate2_flags("dram_root_clk", "dram_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) 	hws[IMX7D_DRAM_PHYM_ROOT_CLK] = imx_clk_hw_gate2_flags("dram_phym_root_clk", "dram_phym_cg", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) 	hws[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_hw_gate2_flags("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) 	hws[IMX7D_DRAM_ALT_ROOT_CLK] = imx_clk_hw_gate2_flags("dram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) 	hws[IMX7D_OCOTP_CLK] = imx_clk_hw_gate4("ocotp_clk", "ipg_root_clk", base + 0x4230, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) 	hws[IMX7D_SNVS_CLK] = imx_clk_hw_gate4("snvs_clk", "ipg_root_clk", base + 0x4250, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) 	hws[IMX7D_MU_ROOT_CLK] = imx_clk_hw_gate4("mu_root_clk", "ipg_root_clk", base + 0x4270, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) 	hws[IMX7D_CAAM_CLK] = imx_clk_hw_gate4("caam_clk", "ipg_root_clk", base + 0x4240, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) 	hws[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_hw_gate4("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4690, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) 	hws[IMX7D_SDMA_CORE_CLK] = imx_clk_hw_gate4("sdma_root_clk", "ahb_root_clk", base + 0x4480, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) 	hws[IMX7D_PCIE_CTRL_ROOT_CLK] = imx_clk_hw_gate4("pcie_ctrl_root_clk", "pcie_ctrl_post_div", base + 0x4600, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) 	hws[IMX7D_PCIE_PHY_ROOT_CLK] = imx_clk_hw_gate4("pcie_phy_root_clk", "pcie_phy_post_div", base + 0x4600, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) 	hws[IMX7D_EPDC_PIXEL_ROOT_CLK] = imx_clk_hw_gate4("epdc_pixel_root_clk", "epdc_pixel_post_div", base + 0x44a0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) 	hws[IMX7D_LCDIF_PIXEL_ROOT_CLK] = imx_clk_hw_gate4("lcdif_pixel_root_clk", "lcdif_pixel_post_div", base + 0x44b0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) 	hws[IMX7D_PXP_CLK] = imx_clk_hw_gate4("pxp_clk", "main_axi_root_clk", base + 0x44c0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) 	hws[IMX7D_MIPI_DSI_ROOT_CLK] = imx_clk_hw_gate4("mipi_dsi_root_clk", "mipi_dsi_post_div", base + 0x4650, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) 	hws[IMX7D_MIPI_CSI_ROOT_CLK] = imx_clk_hw_gate4("mipi_csi_root_clk", "mipi_csi_post_div", base + 0x4640, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) 	hws[IMX7D_MIPI_DPHY_ROOT_CLK] = imx_clk_hw_gate4("mipi_dphy_root_clk", "mipi_dphy_post_div", base + 0x4660, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) 	hws[IMX7D_ENET1_IPG_ROOT_CLK] = imx_clk_hw_gate2_shared2("enet1_ipg_root_clk", "enet_axi_post_div", base + 0x4700, 0, &share_count_enet1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) 	hws[IMX7D_ENET1_TIME_ROOT_CLK] = imx_clk_hw_gate2_shared2("enet1_time_root_clk", "enet1_time_post_div", base + 0x4700, 0, &share_count_enet1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) 	hws[IMX7D_ENET2_IPG_ROOT_CLK] = imx_clk_hw_gate2_shared2("enet2_ipg_root_clk", "enet_axi_post_div", base + 0x4710, 0, &share_count_enet2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) 	hws[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_hw_gate2_shared2("enet2_time_root_clk", "enet2_time_post_div", base + 0x4710, 0, &share_count_enet2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) 	hws[IMX7D_SAI1_ROOT_CLK] = imx_clk_hw_gate2_shared2("sai1_root_clk", "sai1_post_div", base + 0x48c0, 0, &share_count_sai1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) 	hws[IMX7D_SAI1_IPG_CLK]  = imx_clk_hw_gate2_shared2("sai1_ipg_clk",  "ipg_root_clk",  base + 0x48c0, 0, &share_count_sai1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) 	hws[IMX7D_SAI2_ROOT_CLK] = imx_clk_hw_gate2_shared2("sai2_root_clk", "sai2_post_div", base + 0x48d0, 0, &share_count_sai2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) 	hws[IMX7D_SAI2_IPG_CLK]  = imx_clk_hw_gate2_shared2("sai2_ipg_clk",  "ipg_root_clk",  base + 0x48d0, 0, &share_count_sai2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) 	hws[IMX7D_SAI3_ROOT_CLK] = imx_clk_hw_gate2_shared2("sai3_root_clk", "sai3_post_div", base + 0x48e0, 0, &share_count_sai3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) 	hws[IMX7D_SAI3_IPG_CLK]  = imx_clk_hw_gate2_shared2("sai3_ipg_clk",  "ipg_root_clk",  base + 0x48e0, 0, &share_count_sai3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) 	hws[IMX7D_SPDIF_ROOT_CLK] = imx_clk_hw_gate4("spdif_root_clk", "spdif_post_div", base + 0x44d0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) 	hws[IMX7D_EIM_ROOT_CLK] = imx_clk_hw_gate4("eim_root_clk", "eim_post_div", base + 0x4160, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) 	hws[IMX7D_NAND_RAWNAND_CLK] = imx_clk_hw_gate2_shared2("nand_rawnand_clk", "nand_root_clk", base + 0x4140, 0, &share_count_nand);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) 	hws[IMX7D_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_hw_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_root_clk", base + 0x4140, 0, &share_count_nand);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) 	hws[IMX7D_QSPI_ROOT_CLK] = imx_clk_hw_gate4("qspi_root_clk", "qspi_post_div", base + 0x4150, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) 	hws[IMX7D_USDHC1_ROOT_CLK] = imx_clk_hw_gate4("usdhc1_root_clk", "usdhc1_post_div", base + 0x46c0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) 	hws[IMX7D_USDHC2_ROOT_CLK] = imx_clk_hw_gate4("usdhc2_root_clk", "usdhc2_post_div", base + 0x46d0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) 	hws[IMX7D_USDHC3_ROOT_CLK] = imx_clk_hw_gate4("usdhc3_root_clk", "usdhc3_post_div", base + 0x46e0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) 	hws[IMX7D_CAN1_ROOT_CLK] = imx_clk_hw_gate4("can1_root_clk", "can1_post_div", base + 0x4740, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) 	hws[IMX7D_CAN2_ROOT_CLK] = imx_clk_hw_gate4("can2_root_clk", "can2_post_div", base + 0x4750, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) 	hws[IMX7D_I2C1_ROOT_CLK] = imx_clk_hw_gate4("i2c1_root_clk", "i2c1_post_div", base + 0x4880, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) 	hws[IMX7D_I2C2_ROOT_CLK] = imx_clk_hw_gate4("i2c2_root_clk", "i2c2_post_div", base + 0x4890, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) 	hws[IMX7D_I2C3_ROOT_CLK] = imx_clk_hw_gate4("i2c3_root_clk", "i2c3_post_div", base + 0x48a0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) 	hws[IMX7D_I2C4_ROOT_CLK] = imx_clk_hw_gate4("i2c4_root_clk", "i2c4_post_div", base + 0x48b0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) 	hws[IMX7D_UART1_ROOT_CLK] = imx_clk_hw_gate4("uart1_root_clk", "uart1_post_div", base + 0x4940, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) 	hws[IMX7D_UART2_ROOT_CLK] = imx_clk_hw_gate4("uart2_root_clk", "uart2_post_div", base + 0x4950, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) 	hws[IMX7D_UART3_ROOT_CLK] = imx_clk_hw_gate4("uart3_root_clk", "uart3_post_div", base + 0x4960, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) 	hws[IMX7D_UART4_ROOT_CLK] = imx_clk_hw_gate4("uart4_root_clk", "uart4_post_div", base + 0x4970, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) 	hws[IMX7D_UART5_ROOT_CLK] = imx_clk_hw_gate4("uart5_root_clk", "uart5_post_div", base + 0x4980, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) 	hws[IMX7D_UART6_ROOT_CLK] = imx_clk_hw_gate4("uart6_root_clk", "uart6_post_div", base + 0x4990, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) 	hws[IMX7D_UART7_ROOT_CLK] = imx_clk_hw_gate4("uart7_root_clk", "uart7_post_div", base + 0x49a0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) 	hws[IMX7D_ECSPI1_ROOT_CLK] = imx_clk_hw_gate4("ecspi1_root_clk", "ecspi1_post_div", base + 0x4780, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) 	hws[IMX7D_ECSPI2_ROOT_CLK] = imx_clk_hw_gate4("ecspi2_root_clk", "ecspi2_post_div", base + 0x4790, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) 	hws[IMX7D_ECSPI3_ROOT_CLK] = imx_clk_hw_gate4("ecspi3_root_clk", "ecspi3_post_div", base + 0x47a0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) 	hws[IMX7D_ECSPI4_ROOT_CLK] = imx_clk_hw_gate4("ecspi4_root_clk", "ecspi4_post_div", base + 0x47b0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) 	hws[IMX7D_PWM1_ROOT_CLK] = imx_clk_hw_gate4("pwm1_root_clk", "pwm1_post_div", base + 0x4840, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) 	hws[IMX7D_PWM2_ROOT_CLK] = imx_clk_hw_gate4("pwm2_root_clk", "pwm2_post_div", base + 0x4850, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) 	hws[IMX7D_PWM3_ROOT_CLK] = imx_clk_hw_gate4("pwm3_root_clk", "pwm3_post_div", base + 0x4860, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) 	hws[IMX7D_PWM4_ROOT_CLK] = imx_clk_hw_gate4("pwm4_root_clk", "pwm4_post_div", base + 0x4870, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) 	hws[IMX7D_FLEXTIMER1_ROOT_CLK] = imx_clk_hw_gate4("flextimer1_root_clk", "flextimer1_post_div", base + 0x4800, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) 	hws[IMX7D_FLEXTIMER2_ROOT_CLK] = imx_clk_hw_gate4("flextimer2_root_clk", "flextimer2_post_div", base + 0x4810, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) 	hws[IMX7D_SIM1_ROOT_CLK] = imx_clk_hw_gate4("sim1_root_clk", "sim1_post_div", base + 0x4900, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) 	hws[IMX7D_SIM2_ROOT_CLK] = imx_clk_hw_gate4("sim2_root_clk", "sim2_post_div", base + 0x4910, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) 	hws[IMX7D_GPT1_ROOT_CLK] = imx_clk_hw_gate4("gpt1_root_clk", "gpt1_post_div", base + 0x47c0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) 	hws[IMX7D_GPT2_ROOT_CLK] = imx_clk_hw_gate4("gpt2_root_clk", "gpt2_post_div", base + 0x47d0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) 	hws[IMX7D_GPT3_ROOT_CLK] = imx_clk_hw_gate4("gpt3_root_clk", "gpt3_post_div", base + 0x47e0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) 	hws[IMX7D_GPT4_ROOT_CLK] = imx_clk_hw_gate4("gpt4_root_clk", "gpt4_post_div", base + 0x47f0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) 	hws[IMX7D_TRACE_ROOT_CLK] = imx_clk_hw_gate4("trace_root_clk", "trace_post_div", base + 0x4300, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) 	hws[IMX7D_WDOG1_ROOT_CLK] = imx_clk_hw_gate4("wdog1_root_clk", "wdog_post_div", base + 0x49c0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) 	hws[IMX7D_WDOG2_ROOT_CLK] = imx_clk_hw_gate4("wdog2_root_clk", "wdog_post_div", base + 0x49d0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) 	hws[IMX7D_WDOG3_ROOT_CLK] = imx_clk_hw_gate4("wdog3_root_clk", "wdog_post_div", base + 0x49e0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) 	hws[IMX7D_WDOG4_ROOT_CLK] = imx_clk_hw_gate4("wdog4_root_clk", "wdog_post_div", base + 0x49f0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) 	hws[IMX7D_KPP_ROOT_CLK] = imx_clk_hw_gate4("kpp_root_clk", "ipg_root_clk", base + 0x4aa0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) 	hws[IMX7D_CSI_MCLK_ROOT_CLK] = imx_clk_hw_gate4("csi_mclk_root_clk", "csi_mclk_post_div", base + 0x4490, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) 	hws[IMX7D_WRCLK_ROOT_CLK] = imx_clk_hw_gate4("wrclk_root_clk", "wrclk_post_div", base + 0x47a0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) 	hws[IMX7D_USB_CTRL_CLK] = imx_clk_hw_gate4("usb_ctrl_clk", "ahb_root_clk", base + 0x4680, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) 	hws[IMX7D_USB_PHY1_CLK] = imx_clk_hw_gate4("usb_phy1_clk", "pll_usb1_main_clk", base + 0x46a0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) 	hws[IMX7D_USB_PHY2_CLK] = imx_clk_hw_gate4("usb_phy2_clk", "pll_usb_main_clk", base + 0x46b0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) 	hws[IMX7D_ADC_ROOT_CLK] = imx_clk_hw_gate4("adc_root_clk", "ipg_root_clk", base + 0x4200, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) 	hws[IMX7D_GPT_3M_CLK] = imx_clk_hw_fixed_factor("gpt_3m", "osc", 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) 	hws[IMX7D_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a7_root_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) 					 hws[IMX7D_ARM_A7_ROOT_CLK]->clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) 					 hws[IMX7D_ARM_A7_ROOT_SRC]->clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) 					 hws[IMX7D_PLL_ARM_MAIN_CLK]->clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) 					 hws[IMX7D_PLL_SYS_MAIN_CLK]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) 	imx_check_clk_hws(hws, IMX7D_CLK_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) 	of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) 	clk_set_parent(hws[IMX7D_PLL_ARM_MAIN_BYPASS]->clk, hws[IMX7D_PLL_ARM_MAIN]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) 	clk_set_parent(hws[IMX7D_PLL_DRAM_MAIN_BYPASS]->clk, hws[IMX7D_PLL_DRAM_MAIN]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) 	clk_set_parent(hws[IMX7D_PLL_SYS_MAIN_BYPASS]->clk, hws[IMX7D_PLL_SYS_MAIN]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) 	clk_set_parent(hws[IMX7D_PLL_ENET_MAIN_BYPASS]->clk, hws[IMX7D_PLL_ENET_MAIN]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) 	clk_set_parent(hws[IMX7D_PLL_AUDIO_MAIN_BYPASS]->clk, hws[IMX7D_PLL_AUDIO_MAIN]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) 	clk_set_parent(hws[IMX7D_PLL_VIDEO_MAIN_BYPASS]->clk, hws[IMX7D_PLL_VIDEO_MAIN]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) 	clk_set_parent(hws[IMX7D_MIPI_CSI_ROOT_SRC]->clk, hws[IMX7D_PLL_SYS_PFD3_CLK]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) 	/* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) 	clk_set_parent(hws[IMX7D_GPT1_ROOT_SRC]->clk, hws[IMX7D_OSC_24M_CLK]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) 	/* Set clock rate for USBPHY, the USB_PLL at CCM is from USBOTG2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) 	hws[IMX7D_USB1_MAIN_480M_CLK] = imx_clk_hw_fixed_factor("pll_usb1_main_clk", "osc", 20, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) 	hws[IMX7D_USB_MAIN_480M_CLK] = imx_clk_hw_fixed_factor("pll_usb_main_clk", "osc", 20, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) 	imx_register_uart_clocks(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) CLK_OF_DECLARE(imx7d, "fsl,imx7d-ccm", imx7d_clocks_init);