^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2013-2014 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <dt-bindings/clock/imx6sl-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CCSR 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define BM_CCSR_PLL1_SW_CLK_SEL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CACRR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CDHIPR 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define BM_CDHIPR_ARM_PODF_BUSY BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ARM_WAIT_DIV_396M 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ARM_WAIT_DIV_792M 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ARM_WAIT_DIV_996M 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PLL_ARM 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BM_PLL_ARM_DIV_SELECT 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BM_PLL_ARM_POWERDOWN BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BM_PLL_ARM_ENABLE BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BM_PLL_ARM_LOCK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PLL_ARM_DIV_792M 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static const char *step_sels[] = { "osc", "pll2_pfd2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const char *ocram_alt_sels[] = { "pll2_pfd2", "pll3_pfd1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static const char *ocram_sels[] = { "periph", "ocram_alt_sels", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static const char *pre_periph_sels[] = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static const char *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static const char *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static const char *csi_sels[] = { "osc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static const char *lcdif_axi_sels[] = { "pll2_bus", "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static const char *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static const char *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static const char *perclk_sels[] = { "ipg", "osc", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const char *pxp_axi_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static const char *epdc_axi_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static const char *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static const char *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static const char *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static const char *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static const char *ecspi_sels[] = { "pll3_60m", "osc", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const char *uart_sels[] = { "pll3_80m", "osc", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static const char *lvds_sels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) "pll1_sys", "pll2_bus", "pll2_pfd0", "pll2_pfd1", "pll2_pfd2", "dummy", "pll4_audio", "pll5_video",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) "dummy", "enet_ref", "dummy", "dummy", "pll3_usb_otg", "pll7_usb_host", "pll3_pfd0", "pll3_pfd1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) "pll3_pfd2", "pll3_pfd3", "osc", "dummy", "dummy", "dummy", "dummy", "dummy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", "dummy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static const struct clk_div_table clk_enet_ref_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { .val = 0, .div = 20, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { .val = 1, .div = 10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { .val = 2, .div = 5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { .val = 3, .div = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static const struct clk_div_table post_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { .val = 2, .div = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { .val = 1, .div = 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { .val = 0, .div = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const struct clk_div_table video_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { .val = 0, .div = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { .val = 1, .div = 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { .val = 2, .div = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { .val = 3, .div = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static unsigned int share_count_ssi1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static unsigned int share_count_ssi2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static unsigned int share_count_ssi3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static unsigned int share_count_spdif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static struct clk_hw **hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static struct clk_hw_onecell_data *clk_hw_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void __iomem *ccm_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void __iomem *anatop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * ERR005311 CCM: After exit from WAIT mode, unwanted interrupt(s) taken
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * during WAIT mode entry process could cause cache memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * corruption.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * Software workaround:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * To prevent this issue from occurring, software should ensure that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * ARM to IPG clock ratio is less than 12:5 (that is < 2.4x), before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * entering WAIT mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * This function will set the ARM clk to max value within the 12:5 limit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * As IPG clock is fixed at 66MHz(so ARM freq must not exceed 158.4MHz),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * ARM freq are one of below setpoints: 396MHz, 792MHz and 996MHz, since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * the clk APIs can NOT be called in idle thread(may cause kernel schedule
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * as there is sleep function in PLL wait function), so here we just slow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * down ARM to below freq according to previous freq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * run mode wait mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * 396MHz -> 132MHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * 792MHz -> 158.4MHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * 996MHz -> 142.3MHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int imx6sl_get_arm_divider_for_wait(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (readl_relaxed(ccm_base + CCSR) & BM_CCSR_PLL1_SW_CLK_SEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return ARM_WAIT_DIV_396M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if ((readl_relaxed(anatop_base + PLL_ARM) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) BM_PLL_ARM_DIV_SELECT) == PLL_ARM_DIV_792M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return ARM_WAIT_DIV_792M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return ARM_WAIT_DIV_996M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static void imx6sl_enable_pll_arm(bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static u32 saved_pll_arm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) saved_pll_arm = val = readl_relaxed(anatop_base + PLL_ARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) val |= BM_PLL_ARM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) val &= ~BM_PLL_ARM_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) writel_relaxed(val, anatop_base + PLL_ARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) while (!(readl_relaxed(anatop_base + PLL_ARM) & BM_PLL_ARM_LOCK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) writel_relaxed(saved_pll_arm, anatop_base + PLL_ARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) void imx6sl_set_wait_clk(bool enter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static unsigned long saved_arm_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int arm_div_for_wait = imx6sl_get_arm_divider_for_wait();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * According to hardware design, arm podf change need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * PLL1 clock enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (arm_div_for_wait == ARM_WAIT_DIV_396M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) imx6sl_enable_pll_arm(true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (enter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) saved_arm_div = readl_relaxed(ccm_base + CACRR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) writel_relaxed(arm_div_for_wait, ccm_base + CACRR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) writel_relaxed(saved_arm_div, ccm_base + CACRR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) while (__raw_readl(ccm_base + CDHIPR) & BM_CDHIPR_ARM_PODF_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (arm_div_for_wait == ARM_WAIT_DIV_396M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) imx6sl_enable_pll_arm(false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static void __init imx6sl_clocks_init(struct device_node *ccm_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) IMX6SL_CLK_END), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (WARN_ON(!clk_hw_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) clk_hw_data->num = IMX6SL_CLK_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) hws = clk_hw_data->hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) hws[IMX6SL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) hws[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock_hw("ckil", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) hws[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock_hw("osc", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Clock source from external clock via CLK1 PAD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) hws[IMX6SL_CLK_ANACLK1] = imx_obtain_fixed_clock_hw("anaclk1", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) WARN_ON(!base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) anatop_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) hws[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) hws[IMX6SL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) hws[IMX6SL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) hws[IMX6SL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) hws[IMX6SL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) hws[IMX6SL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) hws[IMX6SL_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* type name parent_name base div_mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) hws[IMX6SL_CLK_PLL1] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll1", "osc", base + 0x00, 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) hws[IMX6SL_CLK_PLL2] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) hws[IMX6SL_CLK_PLL3] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll3", "osc", base + 0x10, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) hws[IMX6SL_CLK_PLL4] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll4", "osc", base + 0x70, 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) hws[IMX6SL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) hws[IMX6SL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) hws[IMX6SL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) hws[IMX6SL_PLL1_BYPASS] = imx_clk_hw_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) hws[IMX6SL_PLL2_BYPASS] = imx_clk_hw_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) hws[IMX6SL_PLL3_BYPASS] = imx_clk_hw_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) hws[IMX6SL_PLL4_BYPASS] = imx_clk_hw_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) hws[IMX6SL_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) hws[IMX6SL_PLL6_BYPASS] = imx_clk_hw_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) hws[IMX6SL_PLL7_BYPASS] = imx_clk_hw_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Do not bypass PLLs initially */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) clk_set_parent(hws[IMX6SL_PLL1_BYPASS]->clk, hws[IMX6SL_CLK_PLL1]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) clk_set_parent(hws[IMX6SL_PLL2_BYPASS]->clk, hws[IMX6SL_CLK_PLL2]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) clk_set_parent(hws[IMX6SL_PLL3_BYPASS]->clk, hws[IMX6SL_CLK_PLL3]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) clk_set_parent(hws[IMX6SL_PLL4_BYPASS]->clk, hws[IMX6SL_CLK_PLL4]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) clk_set_parent(hws[IMX6SL_PLL5_BYPASS]->clk, hws[IMX6SL_CLK_PLL5]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) clk_set_parent(hws[IMX6SL_PLL6_BYPASS]->clk, hws[IMX6SL_CLK_PLL6]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) clk_set_parent(hws[IMX6SL_PLL7_BYPASS]->clk, hws[IMX6SL_CLK_PLL7]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) hws[IMX6SL_CLK_PLL1_SYS] = imx_clk_hw_gate("pll1_sys", "pll1_bypass", base + 0x00, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) hws[IMX6SL_CLK_PLL2_BUS] = imx_clk_hw_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) hws[IMX6SL_CLK_PLL3_USB_OTG] = imx_clk_hw_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) hws[IMX6SL_CLK_PLL4_AUDIO] = imx_clk_hw_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) hws[IMX6SL_CLK_PLL5_VIDEO] = imx_clk_hw_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) hws[IMX6SL_CLK_PLL6_ENET] = imx_clk_hw_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) hws[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_hw_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) hws[IMX6SL_CLK_LVDS1_SEL] = imx_clk_hw_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) hws[IMX6SL_CLK_LVDS1_OUT] = imx_clk_hw_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) hws[IMX6SL_CLK_LVDS1_IN] = imx_clk_hw_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * usbphy1 and usbphy2 are implemented as dummy gates using reserve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * bit 20. They are used by phy driver to keep the refcount of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * parent PLL correct. usbphy1_gate and usbphy2_gate only needs to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * turned on during boot, and software will not need to control it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * anymore after that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) hws[IMX6SL_CLK_USBPHY1] = imx_clk_hw_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) hws[IMX6SL_CLK_USBPHY2] = imx_clk_hw_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) hws[IMX6SL_CLK_USBPHY1_GATE] = imx_clk_hw_gate("usbphy1_gate", "dummy", base + 0x10, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) hws[IMX6SL_CLK_USBPHY2_GATE] = imx_clk_hw_gate("usbphy2_gate", "dummy", base + 0x20, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* dev name parent_name flags reg shift width div: flags, div_table lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) hws[IMX6SL_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) hws[IMX6SL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) hws[IMX6SL_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) hws[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) hws[IMX6SL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* name parent_name reg idx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) hws[IMX6SL_CLK_PLL2_PFD0] = imx_clk_hw_pfd("pll2_pfd0", "pll2_bus", base + 0x100, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) hws[IMX6SL_CLK_PLL2_PFD1] = imx_clk_hw_pfd("pll2_pfd1", "pll2_bus", base + 0x100, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) hws[IMX6SL_CLK_PLL2_PFD2] = imx_clk_hw_pfd("pll2_pfd2", "pll2_bus", base + 0x100, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) hws[IMX6SL_CLK_PLL3_PFD0] = imx_clk_hw_pfd("pll3_pfd0", "pll3_usb_otg", base + 0xf0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) hws[IMX6SL_CLK_PLL3_PFD1] = imx_clk_hw_pfd("pll3_pfd1", "pll3_usb_otg", base + 0xf0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) hws[IMX6SL_CLK_PLL3_PFD2] = imx_clk_hw_pfd("pll3_pfd2", "pll3_usb_otg", base + 0xf0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) hws[IMX6SL_CLK_PLL3_PFD3] = imx_clk_hw_pfd("pll3_pfd3", "pll3_usb_otg", base + 0xf0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* name parent_name mult div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) hws[IMX6SL_CLK_PLL2_198M] = imx_clk_hw_fixed_factor("pll2_198m", "pll2_pfd2", 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) hws[IMX6SL_CLK_PLL3_120M] = imx_clk_hw_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) hws[IMX6SL_CLK_PLL3_80M] = imx_clk_hw_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) hws[IMX6SL_CLK_PLL3_60M] = imx_clk_hw_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) np = ccm_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) WARN_ON(!base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ccm_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* name reg shift width parent_names num_parents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) hws[IMX6SL_CLK_STEP] = imx_clk_hw_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) hws[IMX6SL_CLK_PLL1_SW] = imx_clk_hw_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) hws[IMX6SL_CLK_OCRAM_ALT_SEL] = imx_clk_hw_mux("ocram_alt_sel", base + 0x14, 7, 1, ocram_alt_sels, ARRAY_SIZE(ocram_alt_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) hws[IMX6SL_CLK_OCRAM_SEL] = imx_clk_hw_mux("ocram_sel", base + 0x14, 6, 1, ocram_sels, ARRAY_SIZE(ocram_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) hws[IMX6SL_CLK_PRE_PERIPH2_SEL] = imx_clk_hw_mux("pre_periph2_sel", base + 0x18, 21, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) hws[IMX6SL_CLK_PRE_PERIPH_SEL] = imx_clk_hw_mux("pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) hws[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_hw_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) hws[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_hw_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) hws[IMX6SL_CLK_CSI_SEL] = imx_clk_hw_mux("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) hws[IMX6SL_CLK_LCDIF_AXI_SEL] = imx_clk_hw_mux("lcdif_axi_sel", base + 0x3c, 14, 2, lcdif_axi_sels, ARRAY_SIZE(lcdif_axi_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) hws[IMX6SL_CLK_USDHC1_SEL] = imx_clk_hw_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) hws[IMX6SL_CLK_USDHC2_SEL] = imx_clk_hw_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) hws[IMX6SL_CLK_USDHC3_SEL] = imx_clk_hw_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) hws[IMX6SL_CLK_USDHC4_SEL] = imx_clk_hw_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) hws[IMX6SL_CLK_SSI1_SEL] = imx_clk_hw_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) hws[IMX6SL_CLK_SSI2_SEL] = imx_clk_hw_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) hws[IMX6SL_CLK_SSI3_SEL] = imx_clk_hw_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) hws[IMX6SL_CLK_PERCLK_SEL] = imx_clk_hw_fixup_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels), imx_cscmr1_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) hws[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_hw_mux("pxp_axi_sel", base + 0x34, 6, 3, pxp_axi_sels, ARRAY_SIZE(pxp_axi_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) hws[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_hw_mux("epdc_axi_sel", base + 0x34, 15, 3, epdc_axi_sels, ARRAY_SIZE(epdc_axi_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) hws[IMX6SL_CLK_GPU2D_OVG_SEL] = imx_clk_hw_mux("gpu2d_ovg_sel", base + 0x18, 4, 2, gpu2d_ovg_sels, ARRAY_SIZE(gpu2d_ovg_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) hws[IMX6SL_CLK_GPU2D_SEL] = imx_clk_hw_mux("gpu2d_sel", base + 0x18, 8, 2, gpu2d_sels, ARRAY_SIZE(gpu2d_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) hws[IMX6SL_CLK_LCDIF_PIX_SEL] = imx_clk_hw_mux("lcdif_pix_sel", base + 0x38, 6, 3, lcdif_pix_sels, ARRAY_SIZE(lcdif_pix_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) hws[IMX6SL_CLK_EPDC_PIX_SEL] = imx_clk_hw_mux("epdc_pix_sel", base + 0x38, 15, 3, epdc_pix_sels, ARRAY_SIZE(epdc_pix_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) hws[IMX6SL_CLK_SPDIF0_SEL] = imx_clk_hw_mux("spdif0_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) hws[IMX6SL_CLK_SPDIF1_SEL] = imx_clk_hw_mux("spdif1_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) hws[IMX6SL_CLK_EXTERN_AUDIO_SEL] = imx_clk_hw_mux("extern_audio_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) hws[IMX6SL_CLK_ECSPI_SEL] = imx_clk_hw_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) hws[IMX6SL_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* name reg shift width busy: reg, shift parent_names num_parents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) hws[IMX6SL_CLK_PERIPH] = imx_clk_hw_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) hws[IMX6SL_CLK_PERIPH2] = imx_clk_hw_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* name parent_name reg shift width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) hws[IMX6SL_CLK_OCRAM_PODF] = imx_clk_hw_busy_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3, base + 0x48, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) hws[IMX6SL_CLK_PERIPH_CLK2_PODF] = imx_clk_hw_divider("periph_clk2_podf", "periph_clk2_sel", base + 0x14, 27, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) hws[IMX6SL_CLK_PERIPH2_CLK2_PODF] = imx_clk_hw_divider("periph2_clk2_podf", "periph2_clk2_sel", base + 0x14, 0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) hws[IMX6SL_CLK_IPG] = imx_clk_hw_divider("ipg", "ahb", base + 0x14, 8, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) hws[IMX6SL_CLK_CSI_PODF] = imx_clk_hw_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) hws[IMX6SL_CLK_LCDIF_AXI_PODF] = imx_clk_hw_divider("lcdif_axi_podf", "lcdif_axi_sel", base + 0x3c, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) hws[IMX6SL_CLK_USDHC1_PODF] = imx_clk_hw_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) hws[IMX6SL_CLK_USDHC2_PODF] = imx_clk_hw_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) hws[IMX6SL_CLK_USDHC3_PODF] = imx_clk_hw_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) hws[IMX6SL_CLK_USDHC4_PODF] = imx_clk_hw_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) hws[IMX6SL_CLK_SSI1_PRED] = imx_clk_hw_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) hws[IMX6SL_CLK_SSI1_PODF] = imx_clk_hw_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) hws[IMX6SL_CLK_SSI2_PRED] = imx_clk_hw_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) hws[IMX6SL_CLK_SSI2_PODF] = imx_clk_hw_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) hws[IMX6SL_CLK_SSI3_PRED] = imx_clk_hw_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) hws[IMX6SL_CLK_SSI3_PODF] = imx_clk_hw_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) hws[IMX6SL_CLK_PERCLK] = imx_clk_hw_fixup_divider("perclk", "perclk_sel", base + 0x1c, 0, 6, imx_cscmr1_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) hws[IMX6SL_CLK_PXP_AXI_PODF] = imx_clk_hw_divider("pxp_axi_podf", "pxp_axi_sel", base + 0x34, 3, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) hws[IMX6SL_CLK_EPDC_AXI_PODF] = imx_clk_hw_divider("epdc_axi_podf", "epdc_axi_sel", base + 0x34, 12, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) hws[IMX6SL_CLK_GPU2D_OVG_PODF] = imx_clk_hw_divider("gpu2d_ovg_podf", "gpu2d_ovg_sel", base + 0x18, 26, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) hws[IMX6SL_CLK_GPU2D_PODF] = imx_clk_hw_divider("gpu2d_podf", "gpu2d_sel", base + 0x18, 29, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) hws[IMX6SL_CLK_LCDIF_PIX_PRED] = imx_clk_hw_divider("lcdif_pix_pred", "lcdif_pix_sel", base + 0x38, 3, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) hws[IMX6SL_CLK_EPDC_PIX_PRED] = imx_clk_hw_divider("epdc_pix_pred", "epdc_pix_sel", base + 0x38, 12, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) hws[IMX6SL_CLK_LCDIF_PIX_PODF] = imx_clk_hw_fixup_divider("lcdif_pix_podf", "lcdif_pix_pred", base + 0x1c, 20, 3, imx_cscmr1_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) hws[IMX6SL_CLK_EPDC_PIX_PODF] = imx_clk_hw_divider("epdc_pix_podf", "epdc_pix_pred", base + 0x18, 23, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) hws[IMX6SL_CLK_SPDIF0_PRED] = imx_clk_hw_divider("spdif0_pred", "spdif0_sel", base + 0x30, 25, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) hws[IMX6SL_CLK_SPDIF0_PODF] = imx_clk_hw_divider("spdif0_podf", "spdif0_pred", base + 0x30, 22, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) hws[IMX6SL_CLK_SPDIF1_PRED] = imx_clk_hw_divider("spdif1_pred", "spdif1_sel", base + 0x30, 12, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) hws[IMX6SL_CLK_SPDIF1_PODF] = imx_clk_hw_divider("spdif1_podf", "spdif1_pred", base + 0x30, 9, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) hws[IMX6SL_CLK_EXTERN_AUDIO_PRED] = imx_clk_hw_divider("extern_audio_pred", "extern_audio_sel", base + 0x28, 9, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) hws[IMX6SL_CLK_EXTERN_AUDIO_PODF] = imx_clk_hw_divider("extern_audio_podf", "extern_audio_pred", base + 0x28, 25, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) hws[IMX6SL_CLK_ECSPI_ROOT] = imx_clk_hw_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) hws[IMX6SL_CLK_UART_ROOT] = imx_clk_hw_divider("uart_root", "uart_sel", base + 0x24, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* name parent_name reg shift width busy: reg, shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) hws[IMX6SL_CLK_AHB] = imx_clk_hw_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) hws[IMX6SL_CLK_MMDC_ROOT] = imx_clk_hw_busy_divider("mmdc", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) hws[IMX6SL_CLK_ARM] = imx_clk_hw_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* name parent_name reg shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) hws[IMX6SL_CLK_ECSPI1] = imx_clk_hw_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) hws[IMX6SL_CLK_ECSPI2] = imx_clk_hw_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) hws[IMX6SL_CLK_ECSPI3] = imx_clk_hw_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) hws[IMX6SL_CLK_ECSPI4] = imx_clk_hw_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) hws[IMX6SL_CLK_ENET] = imx_clk_hw_gate2("enet", "ipg", base + 0x6c, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) hws[IMX6SL_CLK_EPIT1] = imx_clk_hw_gate2("epit1", "perclk", base + 0x6c, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) hws[IMX6SL_CLK_EPIT2] = imx_clk_hw_gate2("epit2", "perclk", base + 0x6c, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) hws[IMX6SL_CLK_EXTERN_AUDIO] = imx_clk_hw_gate2("extern_audio", "extern_audio_podf", base + 0x6c, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) hws[IMX6SL_CLK_GPT] = imx_clk_hw_gate2("gpt", "perclk", base + 0x6c, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) hws[IMX6SL_CLK_GPT_SERIAL] = imx_clk_hw_gate2("gpt_serial", "perclk", base + 0x6c, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) hws[IMX6SL_CLK_GPU2D_OVG] = imx_clk_hw_gate2("gpu2d_ovg", "gpu2d_ovg_podf", base + 0x6c, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) hws[IMX6SL_CLK_I2C1] = imx_clk_hw_gate2("i2c1", "perclk", base + 0x70, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) hws[IMX6SL_CLK_I2C2] = imx_clk_hw_gate2("i2c2", "perclk", base + 0x70, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) hws[IMX6SL_CLK_I2C3] = imx_clk_hw_gate2("i2c3", "perclk", base + 0x70, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) hws[IMX6SL_CLK_OCOTP] = imx_clk_hw_gate2("ocotp", "ipg", base + 0x70, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) hws[IMX6SL_CLK_CSI] = imx_clk_hw_gate2("csi", "csi_podf", base + 0x74, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) hws[IMX6SL_CLK_PXP_AXI] = imx_clk_hw_gate2("pxp_axi", "pxp_axi_podf", base + 0x74, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) hws[IMX6SL_CLK_EPDC_AXI] = imx_clk_hw_gate2("epdc_axi", "epdc_axi_podf", base + 0x74, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) hws[IMX6SL_CLK_LCDIF_AXI] = imx_clk_hw_gate2("lcdif_axi", "lcdif_axi_podf", base + 0x74, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) hws[IMX6SL_CLK_LCDIF_PIX] = imx_clk_hw_gate2("lcdif_pix", "lcdif_pix_podf", base + 0x74, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) hws[IMX6SL_CLK_EPDC_PIX] = imx_clk_hw_gate2("epdc_pix", "epdc_pix_podf", base + 0x74, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) hws[IMX6SL_CLK_MMDC_P0_IPG] = imx_clk_hw_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) hws[IMX6SL_CLK_MMDC_P1_IPG] = imx_clk_hw_gate2("mmdc_p1_ipg", "ipg", base + 0x74, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) hws[IMX6SL_CLK_OCRAM] = imx_clk_hw_gate2("ocram", "ocram_podf", base + 0x74, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) hws[IMX6SL_CLK_PWM1] = imx_clk_hw_gate2("pwm1", "perclk", base + 0x78, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) hws[IMX6SL_CLK_PWM2] = imx_clk_hw_gate2("pwm2", "perclk", base + 0x78, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) hws[IMX6SL_CLK_PWM3] = imx_clk_hw_gate2("pwm3", "perclk", base + 0x78, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) hws[IMX6SL_CLK_PWM4] = imx_clk_hw_gate2("pwm4", "perclk", base + 0x78, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) hws[IMX6SL_CLK_SDMA] = imx_clk_hw_gate2("sdma", "ipg", base + 0x7c, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) hws[IMX6SL_CLK_SPBA] = imx_clk_hw_gate2("spba", "ipg", base + 0x7c, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) hws[IMX6SL_CLK_SPDIF] = imx_clk_hw_gate2_shared("spdif", "spdif0_podf", base + 0x7c, 14, &share_count_spdif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) hws[IMX6SL_CLK_SPDIF_GCLK] = imx_clk_hw_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) hws[IMX6SL_CLK_SSI1_IPG] = imx_clk_hw_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) hws[IMX6SL_CLK_SSI2_IPG] = imx_clk_hw_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) hws[IMX6SL_CLK_SSI3_IPG] = imx_clk_hw_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) hws[IMX6SL_CLK_SSI1] = imx_clk_hw_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) hws[IMX6SL_CLK_SSI2] = imx_clk_hw_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) hws[IMX6SL_CLK_SSI3] = imx_clk_hw_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) hws[IMX6SL_CLK_UART] = imx_clk_hw_gate2("uart", "ipg", base + 0x7c, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) hws[IMX6SL_CLK_UART_SERIAL] = imx_clk_hw_gate2("uart_serial", "uart_root", base + 0x7c, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) hws[IMX6SL_CLK_USBOH3] = imx_clk_hw_gate2("usboh3", "ipg", base + 0x80, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) hws[IMX6SL_CLK_USDHC1] = imx_clk_hw_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) hws[IMX6SL_CLK_USDHC2] = imx_clk_hw_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) hws[IMX6SL_CLK_USDHC3] = imx_clk_hw_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) hws[IMX6SL_CLK_USDHC4] = imx_clk_hw_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* Ensure the MMDC CH0 handshake is bypassed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) imx_mmdc_mask_handshake(base, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) imx_check_clk_hws(hws, IMX6SL_CLK_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Ensure the AHB clk is at 132MHz. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ret = clk_set_rate(hws[IMX6SL_CLK_AHB]->clk, 132000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) pr_warn("%s: failed to set AHB clock rate %d!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) clk_prepare_enable(hws[IMX6SL_CLK_USBPHY1_GATE]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) clk_prepare_enable(hws[IMX6SL_CLK_USBPHY2_GATE]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* Audio-related clocks configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) clk_set_parent(hws[IMX6SL_CLK_SPDIF0_SEL]->clk, hws[IMX6SL_CLK_PLL3_PFD3]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* set PLL5 video as lcdif pix parent clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) clk_set_parent(hws[IMX6SL_CLK_LCDIF_PIX_SEL]->clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) hws[IMX6SL_CLK_PLL5_VIDEO_DIV]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) clk_set_parent(hws[IMX6SL_CLK_LCDIF_AXI_SEL]->clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) hws[IMX6SL_CLK_PLL2_PFD2]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) imx_register_uart_clocks(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags