^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2011-2013 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2011 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <soc/imx/revision.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <dt-bindings/clock/imx6qdl-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static const char *gpu_axi_sels[] = { "axi", "ahb", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static const char *pre_axi_sels[] = { "axi", "ahb", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const char *gpu2d_core_sels_2[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static const char *ldb_di_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static const char *ipu1_di0_sels_2[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static const char *ipu1_di1_sels_2[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const char *ipu2_di0_sels_2[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static const char *ipu2_di1_sels_2[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static const char *pcie_axi_sels[] = { "axi", "ahb", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static const char *enfc_sels_2[] = {"pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd3_454m", "dummy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const char *eim_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static const char *eim_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static const char *vdo_axi_sels[] = { "axi", "ahb", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static const char *uart_sels[] = { "pll3_80m", "osc", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static const char *ipg_per_sels[] = { "ipg", "osc", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static const char *ecspi_sels[] = { "pll3_60m", "osc", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static const char *can_sels[] = { "pll3_60m", "osc", "pll3_80m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) "video_27m", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static const char *cko2_sels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) "mmdc_ch0_axi", "mmdc_ch1_axi", "usdhc4", "usdhc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "gpu2d_axi", "dummy", "ecspi_root", "gpu3d_axi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) "usdhc3", "dummy", "arm", "ipu1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) "ipu2", "vdo_axi", "osc", "gpu2d_core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) "gpu3d_core", "usdhc2", "ssi1", "ssi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) "ssi3", "gpu3d_shader", "vpu_axi", "can_root",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) "ldb_di0", "ldb_di1", "esai_extal", "eim_slow",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "uart_serial", "spdif", "asrc", "hsi_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static const char *cko_sels[] = { "cko1", "cko2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static const char *lvds_sels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) "dummy", "dummy", "dummy", "dummy", "dummy", "dummy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) "pcie_ref_125m", "sata_ref_100m", "usbphy1", "usbphy2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "dummy", "dummy", "dummy", "dummy", "osc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static struct clk_hw **hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static struct clk_hw_onecell_data *clk_hw_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static struct clk_div_table clk_enet_ref_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { .val = 0, .div = 20, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { .val = 1, .div = 10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { .val = 2, .div = 5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { .val = 3, .div = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static struct clk_div_table post_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { .val = 2, .div = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { .val = 1, .div = 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { .val = 0, .div = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static struct clk_div_table video_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { .val = 0, .div = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { .val = 1, .div = 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { .val = 2, .div = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { .val = 3, .div = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static unsigned int share_count_esai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static unsigned int share_count_asrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static unsigned int share_count_ssi1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static unsigned int share_count_ssi2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static unsigned int share_count_ssi3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static unsigned int share_count_mipi_core_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static unsigned int share_count_spdif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static unsigned int share_count_prg0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static unsigned int share_count_prg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static inline int clk_on_imx6q(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return of_machine_is_compatible("fsl,imx6q");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static inline int clk_on_imx6qp(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return of_machine_is_compatible("fsl,imx6qp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static inline int clk_on_imx6dl(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return of_machine_is_compatible("fsl,imx6dl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int ldb_di_sel_by_clock_id(int clock_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) switch (clock_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) case IMX6QDL_CLK_PLL5_VIDEO_DIV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (clk_on_imx6q() &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) imx_get_soc_revision() == IMX_CHIP_REVISION_1_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) case IMX6QDL_CLK_PLL2_PFD0_352M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) case IMX6QDL_CLK_PLL2_PFD2_396M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) case IMX6QDL_CLK_MMDC_CH1_AXI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) case IMX6QDL_CLK_PLL3_USB_OTG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static void of_assigned_ldb_sels(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned int *ldb_di0_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned int *ldb_di1_sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct of_phandle_args clkspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int index, rc, num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int parent, child, sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) num_parents = of_count_phandle_with_args(node, "assigned-clock-parents",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "#clock-cells");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) for (index = 0; index < num_parents; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) rc = of_parse_phandle_with_args(node, "assigned-clock-parents",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "#clock-cells", index, &clkspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* skip empty (null) phandles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (rc == -ENOENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) pr_err("ccm: parent clock %d not in ccm\n", index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) parent = clkspec.args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) rc = of_parse_phandle_with_args(node, "assigned-clocks",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "#clock-cells", index, &clkspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pr_err("ccm: child clock %d not in ccm\n", index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) child = clkspec.args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (child != IMX6QDL_CLK_LDB_DI0_SEL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) child != IMX6QDL_CLK_LDB_DI1_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) sel = ldb_di_sel_by_clock_id(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (sel < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) pr_err("ccm: invalid ldb_di%d parent clock: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) child == IMX6QDL_CLK_LDB_DI1_SEL, parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (child == IMX6QDL_CLK_LDB_DI0_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) *ldb_di0_sel = sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (child == IMX6QDL_CLK_LDB_DI1_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) *ldb_di1_sel = sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static bool pll6_bypassed(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int index, ret, num_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct of_phandle_args clkspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) num_clocks = of_count_phandle_with_args(node, "assigned-clocks",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) "#clock-cells");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (num_clocks < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) for (index = 0; index < num_clocks; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ret = of_parse_phandle_with_args(node, "assigned-clocks",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) "#clock-cells", index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) &clkspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (clkspec.np == node &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) clkspec.args[0] == IMX6QDL_PLL6_BYPASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* PLL6 bypass is not part of the assigned clock list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (index == num_clocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ret = of_parse_phandle_with_args(node, "assigned-clock-parents",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) "#clock-cells", index, &clkspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (clkspec.args[0] != IMX6QDL_CLK_PLL6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define CCM_CCSR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define CCM_CS2CDR 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define CCSR_PLL3_SW_CLK_SEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define CS2CDR_LDB_DI0_CLK_SEL_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define CS2CDR_LDB_DI1_CLK_SEL_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * The only way to disable the MMDC_CH1 clock is to move it to pll3_sw_clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * via periph2_clk2_sel and then to disable pll3_sw_clk by selecting the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * bypass clock source, since there is no CG bit for mmdc_ch1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static void mmdc_ch1_disable(void __iomem *ccm_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) clk_set_parent(hws[IMX6QDL_CLK_PERIPH2_CLK2_SEL]->clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Disable pll3_sw_clk by selecting the bypass clock source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) reg = readl_relaxed(ccm_base + CCM_CCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) reg |= CCSR_PLL3_SW_CLK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) writel_relaxed(reg, ccm_base + CCM_CCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static void mmdc_ch1_reenable(void __iomem *ccm_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Enable pll3_sw_clk by disabling the bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) reg = readl_relaxed(ccm_base + CCM_CCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) reg &= ~CCSR_PLL3_SW_CLK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) writel_relaxed(reg, ccm_base + CCM_CCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * We have to follow a strict procedure when changing the LDB clock source,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * otherwise we risk introducing a glitch that can lock up the LDB divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * Things to keep in mind:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * 1. The current and new parent clock inputs to the mux must be disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * 2. The default clock input for ldb_di0/1_clk_sel is mmdc_ch1_axi, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * has no CG bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * 3. pll2_pfd2_396m can not be gated if it is used as memory clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * 4. In the RTL implementation of the LDB_DI_CLK_SEL muxes the top four
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * options are in one mux and the PLL3 option along with three unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * inputs is in a second mux. There is a third mux with two inputs used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * to decide between the first and second 4-port mux:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * pll5_video_div 0 --|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * pll2_pfd0_352m 1 --| |_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * pll2_pfd2_396m 2 --| | `-|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * mmdc_ch1_axi 3 --|/ | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * | |--
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * pll3_usb_otg 4 --|\ | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * 5 --| |_,-|/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * 6 --| |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * 7 --|/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * The ldb_di0/1_clk_sel[1:0] bits control both 4-port muxes at the same time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * The ldb_di0/1_clk_sel[2] bit controls the 2-port mux. The code below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * switches the parent to the bottom mux first and then manipulates the top
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * mux to ensure that no glitch will enter the divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static void init_ldb_clks(struct device_node *np, void __iomem *ccm_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned int sel[2][4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) reg = readl_relaxed(ccm_base + CCM_CS2CDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) sel[0][0] = (reg >> CS2CDR_LDB_DI0_CLK_SEL_SHIFT) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) sel[1][0] = (reg >> CS2CDR_LDB_DI1_CLK_SEL_SHIFT) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) sel[0][3] = sel[0][2] = sel[0][1] = sel[0][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) sel[1][3] = sel[1][2] = sel[1][1] = sel[1][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) of_assigned_ldb_sels(np, &sel[0][3], &sel[1][3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Warn if a glitch might have been introduced already */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (sel[i][0] != 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) pr_warn("ccm: ldb_di%d_sel already changed from reset value: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) i, sel[i][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (sel[i][0] == sel[i][3])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* Only switch to or from pll2_pfd2_396m if it is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if ((sel[i][0] == 2 || sel[i][3] == 2) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) (clk_get_parent(hws[IMX6QDL_CLK_PERIPH_PRE]->clk) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) pr_err("ccm: ldb_di%d_sel: couldn't disable pll2_pfd2_396m\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) sel[i][3] = sel[i][2] = sel[i][1] = sel[i][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* First switch to the bottom mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) sel[i][1] = sel[i][0] | 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* Then configure the top mux before switching back to it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) sel[i][2] = sel[i][3] | 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) pr_debug("ccm: switching ldb_di%d_sel: %d->%d->%d->%d\n", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) sel[i][0], sel[i][1], sel[i][2], sel[i][3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (sel[0][0] == sel[0][3] && sel[1][0] == sel[1][3])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) mmdc_ch1_disable(ccm_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) for (i = 1; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) reg = readl_relaxed(ccm_base + CCM_CS2CDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) reg &= ~((7 << CS2CDR_LDB_DI0_CLK_SEL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) (7 << CS2CDR_LDB_DI1_CLK_SEL_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) reg |= ((sel[0][i] << CS2CDR_LDB_DI0_CLK_SEL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) (sel[1][i] << CS2CDR_LDB_DI1_CLK_SEL_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) writel_relaxed(reg, ccm_base + CCM_CS2CDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) mmdc_ch1_reenable(ccm_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define CCM_ANALOG_PLL_VIDEO 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define CCM_ANALOG_PFD_480 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define CCM_ANALOG_PFD_528 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define PLL_ENABLE BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define PFD0_CLKGATE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define PFD1_CLKGATE BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define PFD2_CLKGATE BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define PFD3_CLKGATE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static void disable_anatop_clocks(void __iomem *anatop_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* Make sure PLL2 PFDs 0-2 are gated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_528);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* Cannot gate PFD2 if pll2_pfd2_396m is the parent of MMDC clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (clk_get_parent(hws[IMX6QDL_CLK_PERIPH_PRE]->clk) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) reg |= PFD0_CLKGATE | PFD1_CLKGATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) reg |= PFD0_CLKGATE | PFD1_CLKGATE | PFD2_CLKGATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_528);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* Make sure PLL3 PFDs 0-3 are gated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_480);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) reg |= PFD0_CLKGATE | PFD1_CLKGATE | PFD2_CLKGATE | PFD3_CLKGATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_480);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Make sure PLL5 is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) reg = readl_relaxed(anatop_base + CCM_ANALOG_PLL_VIDEO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) reg &= ~PLL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) writel_relaxed(reg, anatop_base + CCM_ANALOG_PLL_VIDEO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static struct clk_hw * __init imx6q_obtain_fixed_clk_hw(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct clk *clk = of_clk_get_by_name(np, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) hw = imx_obtain_fixed_clock_hw(name, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) hw = __clk_get_hw(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static void __init imx6q_clocks_init(struct device_node *ccm_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) void __iomem *anatop_base, *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) IMX6QDL_CLK_END), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (WARN_ON(!clk_hw_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) clk_hw_data->num = IMX6QDL_CLK_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) hws = clk_hw_data->hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) hws[IMX6QDL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) hws[IMX6QDL_CLK_CKIL] = imx6q_obtain_fixed_clk_hw(ccm_node, "ckil", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) hws[IMX6QDL_CLK_CKIH] = imx6q_obtain_fixed_clk_hw(ccm_node, "ckih1", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) hws[IMX6QDL_CLK_OSC] = imx6q_obtain_fixed_clk_hw(ccm_node, "osc", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* Clock source from external clock via CLK1/2 PADs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) hws[IMX6QDL_CLK_ANACLK1] = imx6q_obtain_fixed_clk_hw(ccm_node, "anaclk1", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) hws[IMX6QDL_CLK_ANACLK2] = imx6q_obtain_fixed_clk_hw(ccm_node, "anaclk2", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) anatop_base = base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) WARN_ON(!base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) post_div_table[1].div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) post_div_table[2].div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) video_div_table[1].div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) video_div_table[3].div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) hws[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) hws[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) hws[IMX6QDL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) hws[IMX6QDL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) hws[IMX6QDL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) hws[IMX6QDL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) hws[IMX6QDL_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base + 0x20, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* type name parent_name base div_mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) hws[IMX6QDL_CLK_PLL1] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll1", "osc", base + 0x00, 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) hws[IMX6QDL_CLK_PLL2] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) hws[IMX6QDL_CLK_PLL3] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll3", "osc", base + 0x10, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) hws[IMX6QDL_CLK_PLL4] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll4", "osc", base + 0x70, 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) hws[IMX6QDL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) hws[IMX6QDL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) hws[IMX6QDL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) hws[IMX6QDL_PLL1_BYPASS] = imx_clk_hw_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) hws[IMX6QDL_PLL2_BYPASS] = imx_clk_hw_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) hws[IMX6QDL_PLL3_BYPASS] = imx_clk_hw_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) hws[IMX6QDL_PLL4_BYPASS] = imx_clk_hw_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) hws[IMX6QDL_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) hws[IMX6QDL_PLL6_BYPASS] = imx_clk_hw_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) hws[IMX6QDL_PLL7_BYPASS] = imx_clk_hw_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* Do not bypass PLLs initially */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) clk_set_parent(hws[IMX6QDL_PLL1_BYPASS]->clk, hws[IMX6QDL_CLK_PLL1]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) clk_set_parent(hws[IMX6QDL_PLL2_BYPASS]->clk, hws[IMX6QDL_CLK_PLL2]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) clk_set_parent(hws[IMX6QDL_PLL3_BYPASS]->clk, hws[IMX6QDL_CLK_PLL3]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) clk_set_parent(hws[IMX6QDL_PLL4_BYPASS]->clk, hws[IMX6QDL_CLK_PLL4]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) clk_set_parent(hws[IMX6QDL_PLL5_BYPASS]->clk, hws[IMX6QDL_CLK_PLL5]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) clk_set_parent(hws[IMX6QDL_PLL6_BYPASS]->clk, hws[IMX6QDL_CLK_PLL6]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) clk_set_parent(hws[IMX6QDL_PLL7_BYPASS]->clk, hws[IMX6QDL_CLK_PLL7]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) hws[IMX6QDL_CLK_PLL1_SYS] = imx_clk_hw_gate("pll1_sys", "pll1_bypass", base + 0x00, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) hws[IMX6QDL_CLK_PLL2_BUS] = imx_clk_hw_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) hws[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_hw_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) hws[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_hw_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) hws[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_hw_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) hws[IMX6QDL_CLK_PLL6_ENET] = imx_clk_hw_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) hws[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_hw_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * Bit 20 is the reserved and read-only bit, we do this only for:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * - Do nothing for usbphy clk_enable/disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * - Keep refcount when do usbphy clk_enable/disable, in that case,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * the clk framework may need to enable/disable usbphy's parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) hws[IMX6QDL_CLK_USBPHY1] = imx_clk_hw_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) hws[IMX6QDL_CLK_USBPHY2] = imx_clk_hw_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * usbphy*_gate needs to be on after system boots up, and software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * never needs to control it anymore.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) hws[IMX6QDL_CLK_USBPHY1_GATE] = imx_clk_hw_gate("usbphy1_gate", "dummy", base + 0x10, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) hws[IMX6QDL_CLK_USBPHY2_GATE] = imx_clk_hw_gate("usbphy2_gate", "dummy", base + 0x20, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * The ENET PLL is special in that is has multiple outputs with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * different post-dividers that are all affected by the single bypass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * bit, so a single mux bit affects 3 independent branches of the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * tree. There is no good way to model this in the clock framework and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * dynamically changing the bypass bit, will yield unexpected results.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * So we treat any configuration that bypasses the ENET PLL as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * essentially static with the divider ratios reflecting the bypass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (!pll6_bypassed(ccm_node)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) hws[IMX6QDL_CLK_SATA_REF] = imx_clk_hw_fixed_factor("sata_ref", "pll6_enet", 1, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) hws[IMX6QDL_CLK_PCIE_REF] = imx_clk_hw_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) hws[IMX6QDL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) base + 0xe0, 0, 2, 0, clk_enet_ref_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) hws[IMX6QDL_CLK_SATA_REF] = imx_clk_hw_fixed_factor("sata_ref", "pll6_enet", 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) hws[IMX6QDL_CLK_PCIE_REF] = imx_clk_hw_fixed_factor("pcie_ref", "pll6_enet", 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) hws[IMX6QDL_CLK_ENET_REF] = imx_clk_hw_fixed_factor("enet_ref", "pll6_enet", 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) hws[IMX6QDL_CLK_SATA_REF_100M] = imx_clk_hw_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) hws[IMX6QDL_CLK_PCIE_REF_125M] = imx_clk_hw_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) hws[IMX6QDL_CLK_LVDS1_SEL] = imx_clk_hw_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) hws[IMX6QDL_CLK_LVDS2_SEL] = imx_clk_hw_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * lvds1_gate and lvds2_gate are pseudo-gates. Both can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * independently configured as clock inputs or outputs. We treat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * the "output_enable" bit as a gate, even though it's really just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * enabling clock output. Initially the gate bits are cleared, as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * otherwise the exclusive configuration gets locked in the setup done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * by software running before the clock driver, with no way to change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) writel(readl(base + 0x160) & ~0x3c00, base + 0x160);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) hws[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_hw_gate_exclusive("lvds1_gate", "lvds1_sel", base + 0x160, 10, BIT(12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) hws[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_hw_gate_exclusive("lvds2_gate", "lvds2_sel", base + 0x160, 11, BIT(13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) hws[IMX6QDL_CLK_LVDS1_IN] = imx_clk_hw_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) hws[IMX6QDL_CLK_LVDS2_IN] = imx_clk_hw_gate_exclusive("lvds2_in", "anaclk2", base + 0x160, 13, BIT(11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* name parent_name reg idx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) hws[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_hw_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) hws[IMX6QDL_CLK_PLL2_PFD1_594M] = imx_clk_hw_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) hws[IMX6QDL_CLK_PLL2_PFD2_396M] = imx_clk_hw_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) hws[IMX6QDL_CLK_PLL3_PFD0_720M] = imx_clk_hw_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) hws[IMX6QDL_CLK_PLL3_PFD1_540M] = imx_clk_hw_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) hws[IMX6QDL_CLK_PLL3_PFD2_508M] = imx_clk_hw_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) hws[IMX6QDL_CLK_PLL3_PFD3_454M] = imx_clk_hw_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* name parent_name mult div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) hws[IMX6QDL_CLK_PLL2_198M] = imx_clk_hw_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) hws[IMX6QDL_CLK_PLL3_120M] = imx_clk_hw_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) hws[IMX6QDL_CLK_PLL3_80M] = imx_clk_hw_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) hws[IMX6QDL_CLK_PLL3_60M] = imx_clk_hw_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) hws[IMX6QDL_CLK_TWD] = imx_clk_hw_fixed_factor("twd", "arm", 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) hws[IMX6QDL_CLK_GPT_3M] = imx_clk_hw_fixed_factor("gpt_3m", "osc", 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) hws[IMX6QDL_CLK_VIDEO_27M] = imx_clk_hw_fixed_factor("video_27m", "pll3_pfd1_540m", 1, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (clk_on_imx6dl() || clk_on_imx6qp()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) hws[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_hw_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) hws[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_hw_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) hws[IMX6QDL_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (clk_on_imx6q() || clk_on_imx6qp())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) hws[IMX6QDL_CLK_PLL4_AUDIO_DIV] = imx_clk_hw_fixed_factor("pll4_audio_div", "pll4_post_div", 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) hws[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) hws[IMX6QDL_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) hws[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) np = ccm_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) WARN_ON(!base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* name reg shift width parent_names num_parents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) hws[IMX6QDL_CLK_STEP] = imx_clk_hw_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) hws[IMX6QDL_CLK_PLL1_SW] = imx_clk_hw_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) hws[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_hw_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) hws[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_hw_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) hws[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_hw_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) hws[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_hw_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) hws[IMX6QDL_CLK_AXI_SEL] = imx_clk_hw_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) hws[IMX6QDL_CLK_ESAI_SEL] = imx_clk_hw_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) hws[IMX6QDL_CLK_ASRC_SEL] = imx_clk_hw_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) hws[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_hw_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (clk_on_imx6q()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) hws[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_hw_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) hws[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_hw_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (clk_on_imx6qp()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) hws[IMX6QDL_CLK_CAN_SEL] = imx_clk_hw_mux("can_sel", base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) hws[IMX6QDL_CLK_ECSPI_SEL] = imx_clk_hw_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) hws[IMX6QDL_CLK_IPG_PER_SEL] = imx_clk_hw_mux("ipg_per_sel", base + 0x1c, 6, 1, ipg_per_sels, ARRAY_SIZE(ipg_per_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) hws[IMX6QDL_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) hws[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_hw_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels_2, ARRAY_SIZE(gpu2d_core_sels_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) } else if (clk_on_imx6dl()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) hws[IMX6QDL_CLK_MLB_SEL] = imx_clk_hw_mux("mlb_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) hws[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_hw_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) hws[IMX6QDL_CLK_GPU3D_CORE_SEL] = imx_clk_hw_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (clk_on_imx6dl())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) hws[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_hw_mux("gpu2d_core_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) hws[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_hw_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) hws[IMX6QDL_CLK_IPU1_SEL] = imx_clk_hw_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) hws[IMX6QDL_CLK_IPU2_SEL] = imx_clk_hw_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) disable_anatop_clocks(anatop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) imx_mmdc_mask_handshake(base, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (clk_on_imx6qp()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) hws[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_hw_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) hws[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_hw_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * The LDB_DI0/1_SEL muxes are registered read-only due to a hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * bug. Set the muxes to the requested values before registering the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * ldb_di_sel clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) init_ldb_clks(np, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) hws[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_hw_mux_ldb("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) hws[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_hw_mux_ldb("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) hws[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_hw_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) hws[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_hw_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) hws[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_hw_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) hws[IMX6QDL_CLK_IPU2_DI1_PRE_SEL] = imx_clk_hw_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) hws[IMX6QDL_CLK_HSI_TX_SEL] = imx_clk_hw_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) hws[IMX6QDL_CLK_PCIE_AXI_SEL] = imx_clk_hw_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (clk_on_imx6qp()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) hws[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_hw_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels_2, ARRAY_SIZE(ipu1_di0_sels_2), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) hws[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_hw_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels_2, ARRAY_SIZE(ipu1_di1_sels_2), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) hws[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_hw_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels_2, ARRAY_SIZE(ipu2_di0_sels_2), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) hws[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_hw_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels_2, ARRAY_SIZE(ipu2_di1_sels_2), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) hws[IMX6QDL_CLK_SSI1_SEL] = imx_clk_hw_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) hws[IMX6QDL_CLK_SSI2_SEL] = imx_clk_hw_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) hws[IMX6QDL_CLK_SSI3_SEL] = imx_clk_hw_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) hws[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_hw_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) hws[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_hw_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) hws[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_hw_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) hws[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_hw_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) hws[IMX6QDL_CLK_ENFC_SEL] = imx_clk_hw_mux("enfc_sel", base + 0x2c, 15, 3, enfc_sels_2, ARRAY_SIZE(enfc_sels_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) hws[IMX6QDL_CLK_EIM_SEL] = imx_clk_hw_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) hws[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_hw_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) hws[IMX6QDL_CLK_PRE_AXI] = imx_clk_hw_mux("pre_axi", base + 0x18, 1, 1, pre_axi_sels, ARRAY_SIZE(pre_axi_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) hws[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_hw_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) hws[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_hw_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) hws[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_hw_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) hws[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_hw_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) hws[IMX6QDL_CLK_SSI1_SEL] = imx_clk_hw_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) hws[IMX6QDL_CLK_SSI2_SEL] = imx_clk_hw_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) hws[IMX6QDL_CLK_SSI3_SEL] = imx_clk_hw_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) hws[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_hw_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) hws[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_hw_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) hws[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_hw_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) hws[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_hw_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) hws[IMX6QDL_CLK_ENFC_SEL] = imx_clk_hw_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) hws[IMX6QDL_CLK_EIM_SEL] = imx_clk_hw_fixup_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels), imx_cscmr1_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) hws[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_hw_fixup_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels), imx_cscmr1_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) hws[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_hw_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) hws[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_hw_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) hws[IMX6QDL_CLK_CKO1_SEL] = imx_clk_hw_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) hws[IMX6QDL_CLK_CKO2_SEL] = imx_clk_hw_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) hws[IMX6QDL_CLK_CKO] = imx_clk_hw_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* name reg shift width busy: reg, shift parent_names num_parents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) hws[IMX6QDL_CLK_PERIPH] = imx_clk_hw_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) hws[IMX6QDL_CLK_PERIPH2] = imx_clk_hw_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /* name parent_name reg shift width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) hws[IMX6QDL_CLK_PERIPH_CLK2] = imx_clk_hw_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) hws[IMX6QDL_CLK_PERIPH2_CLK2] = imx_clk_hw_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) hws[IMX6QDL_CLK_IPG] = imx_clk_hw_divider("ipg", "ahb", base + 0x14, 8, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) hws[IMX6QDL_CLK_ESAI_PRED] = imx_clk_hw_divider("esai_pred", "esai_sel", base + 0x28, 9, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) hws[IMX6QDL_CLK_ESAI_PODF] = imx_clk_hw_divider("esai_podf", "esai_pred", base + 0x28, 25, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) hws[IMX6QDL_CLK_ASRC_PRED] = imx_clk_hw_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) hws[IMX6QDL_CLK_ASRC_PODF] = imx_clk_hw_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) hws[IMX6QDL_CLK_SPDIF_PRED] = imx_clk_hw_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) hws[IMX6QDL_CLK_SPDIF_PODF] = imx_clk_hw_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (clk_on_imx6qp()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) hws[IMX6QDL_CLK_IPG_PER] = imx_clk_hw_divider("ipg_per", "ipg_per_sel", base + 0x1c, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) hws[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_hw_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) hws[IMX6QDL_CLK_CAN_ROOT] = imx_clk_hw_divider("can_root", "can_sel", base + 0x20, 2, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) hws[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_hw_divider("uart_serial_podf", "uart_sel", base + 0x24, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) hws[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di0_div_3_5", "ldb_di0", 2, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) hws[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di1_div_3_5", "ldb_di1", 2, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) hws[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_hw_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) hws[IMX6QDL_CLK_CAN_ROOT] = imx_clk_hw_divider("can_root", "pll3_60m", base + 0x20, 2, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) hws[IMX6QDL_CLK_IPG_PER] = imx_clk_hw_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) hws[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_hw_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) hws[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) hws[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (clk_on_imx6dl())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) hws[IMX6QDL_CLK_MLB_PODF] = imx_clk_hw_divider("mlb_podf", "mlb_sel", base + 0x18, 23, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) hws[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_hw_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) hws[IMX6QDL_CLK_GPU3D_CORE_PODF] = imx_clk_hw_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (clk_on_imx6dl())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) hws[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_hw_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 29, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) hws[IMX6QDL_CLK_GPU3D_SHADER] = imx_clk_hw_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) hws[IMX6QDL_CLK_IPU1_PODF] = imx_clk_hw_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) hws[IMX6QDL_CLK_IPU2_PODF] = imx_clk_hw_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) hws[IMX6QDL_CLK_LDB_DI0_PODF] = imx_clk_hw_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) hws[IMX6QDL_CLK_LDB_DI1_PODF] = imx_clk_hw_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) hws[IMX6QDL_CLK_IPU1_DI0_PRE] = imx_clk_hw_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) hws[IMX6QDL_CLK_IPU1_DI1_PRE] = imx_clk_hw_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) hws[IMX6QDL_CLK_IPU2_DI0_PRE] = imx_clk_hw_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) hws[IMX6QDL_CLK_IPU2_DI1_PRE] = imx_clk_hw_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) hws[IMX6QDL_CLK_HSI_TX_PODF] = imx_clk_hw_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) hws[IMX6QDL_CLK_SSI1_PRED] = imx_clk_hw_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) hws[IMX6QDL_CLK_SSI1_PODF] = imx_clk_hw_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) hws[IMX6QDL_CLK_SSI2_PRED] = imx_clk_hw_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) hws[IMX6QDL_CLK_SSI2_PODF] = imx_clk_hw_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) hws[IMX6QDL_CLK_SSI3_PRED] = imx_clk_hw_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) hws[IMX6QDL_CLK_SSI3_PODF] = imx_clk_hw_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) hws[IMX6QDL_CLK_USDHC1_PODF] = imx_clk_hw_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) hws[IMX6QDL_CLK_USDHC2_PODF] = imx_clk_hw_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) hws[IMX6QDL_CLK_USDHC3_PODF] = imx_clk_hw_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) hws[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_hw_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) hws[IMX6QDL_CLK_ENFC_PRED] = imx_clk_hw_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) hws[IMX6QDL_CLK_ENFC_PODF] = imx_clk_hw_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (clk_on_imx6qp()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) hws[IMX6QDL_CLK_EIM_PODF] = imx_clk_hw_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) hws[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_hw_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) hws[IMX6QDL_CLK_EIM_PODF] = imx_clk_hw_fixup_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) hws[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_hw_fixup_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) hws[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_hw_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) hws[IMX6QDL_CLK_CKO1_PODF] = imx_clk_hw_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) hws[IMX6QDL_CLK_CKO2_PODF] = imx_clk_hw_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* name parent_name reg shift width busy: reg, shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) hws[IMX6QDL_CLK_AXI] = imx_clk_hw_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) hws[IMX6QDL_CLK_MMDC_CH0_AXI_PODF] = imx_clk_hw_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (clk_on_imx6qp()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) hws[IMX6QDL_CLK_MMDC_CH1_AXI_CG] = imx_clk_hw_gate("mmdc_ch1_axi_cg", "periph2", base + 0x4, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) hws[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_hw_busy_divider("mmdc_ch1_axi_podf", "mmdc_ch1_axi_cg", base + 0x14, 3, 3, base + 0x48, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) hws[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_hw_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) hws[IMX6QDL_CLK_ARM] = imx_clk_hw_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) hws[IMX6QDL_CLK_AHB] = imx_clk_hw_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* name parent_name reg shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) hws[IMX6QDL_CLK_APBH_DMA] = imx_clk_hw_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) hws[IMX6QDL_CLK_ASRC] = imx_clk_hw_gate2_shared("asrc", "asrc_podf", base + 0x68, 6, &share_count_asrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) hws[IMX6QDL_CLK_ASRC_IPG] = imx_clk_hw_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) hws[IMX6QDL_CLK_ASRC_MEM] = imx_clk_hw_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) hws[IMX6QDL_CLK_CAAM_MEM] = imx_clk_hw_gate2("caam_mem", "ahb", base + 0x68, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) hws[IMX6QDL_CLK_CAAM_ACLK] = imx_clk_hw_gate2("caam_aclk", "ahb", base + 0x68, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) hws[IMX6QDL_CLK_CAAM_IPG] = imx_clk_hw_gate2("caam_ipg", "ipg", base + 0x68, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) hws[IMX6QDL_CLK_CAN1_IPG] = imx_clk_hw_gate2("can1_ipg", "ipg", base + 0x68, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) hws[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_hw_gate2("can1_serial", "can_root", base + 0x68, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) hws[IMX6QDL_CLK_CAN2_IPG] = imx_clk_hw_gate2("can2_ipg", "ipg", base + 0x68, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) hws[IMX6QDL_CLK_CAN2_SERIAL] = imx_clk_hw_gate2("can2_serial", "can_root", base + 0x68, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) hws[IMX6QDL_CLK_DCIC1] = imx_clk_hw_gate2("dcic1", "ipu1_podf", base + 0x68, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) hws[IMX6QDL_CLK_DCIC2] = imx_clk_hw_gate2("dcic2", "ipu2_podf", base + 0x68, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) hws[IMX6QDL_CLK_ECSPI1] = imx_clk_hw_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) hws[IMX6QDL_CLK_ECSPI2] = imx_clk_hw_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) hws[IMX6QDL_CLK_ECSPI3] = imx_clk_hw_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) hws[IMX6QDL_CLK_ECSPI4] = imx_clk_hw_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (clk_on_imx6dl())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) hws[IMX6DL_CLK_I2C4] = imx_clk_hw_gate2("i2c4", "ipg_per", base + 0x6c, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) hws[IMX6Q_CLK_ECSPI5] = imx_clk_hw_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) hws[IMX6QDL_CLK_ENET] = imx_clk_hw_gate2("enet", "ipg", base + 0x6c, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) hws[IMX6QDL_CLK_EPIT1] = imx_clk_hw_gate2("epit1", "ipg", base + 0x6c, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) hws[IMX6QDL_CLK_EPIT2] = imx_clk_hw_gate2("epit2", "ipg", base + 0x6c, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) hws[IMX6QDL_CLK_ESAI_EXTAL] = imx_clk_hw_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) hws[IMX6QDL_CLK_ESAI_IPG] = imx_clk_hw_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) hws[IMX6QDL_CLK_ESAI_MEM] = imx_clk_hw_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) hws[IMX6QDL_CLK_GPT_IPG] = imx_clk_hw_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) hws[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_hw_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) hws[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_hw_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) hws[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_hw_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) hws[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_hw_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) hws[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_hw_gate2("hdmi_isfr", "mipi_core_cfg", base + 0x70, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) hws[IMX6QDL_CLK_I2C1] = imx_clk_hw_gate2("i2c1", "ipg_per", base + 0x70, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) hws[IMX6QDL_CLK_I2C2] = imx_clk_hw_gate2("i2c2", "ipg_per", base + 0x70, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) hws[IMX6QDL_CLK_I2C3] = imx_clk_hw_gate2("i2c3", "ipg_per", base + 0x70, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) hws[IMX6QDL_CLK_IIM] = imx_clk_hw_gate2("iim", "ipg", base + 0x70, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) hws[IMX6QDL_CLK_ENFC] = imx_clk_hw_gate2("enfc", "enfc_podf", base + 0x70, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) hws[IMX6QDL_CLK_VDOA] = imx_clk_hw_gate2("vdoa", "vdo_axi", base + 0x70, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) hws[IMX6QDL_CLK_IPU1] = imx_clk_hw_gate2("ipu1", "ipu1_podf", base + 0x74, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) hws[IMX6QDL_CLK_IPU1_DI0] = imx_clk_hw_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) hws[IMX6QDL_CLK_IPU1_DI1] = imx_clk_hw_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) hws[IMX6QDL_CLK_IPU2] = imx_clk_hw_gate2("ipu2", "ipu2_podf", base + 0x74, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) hws[IMX6QDL_CLK_IPU2_DI0] = imx_clk_hw_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (clk_on_imx6qp()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) hws[IMX6QDL_CLK_LDB_DI0] = imx_clk_hw_gate2("ldb_di0", "ldb_di0_sel", base + 0x74, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) hws[IMX6QDL_CLK_LDB_DI1] = imx_clk_hw_gate2("ldb_di1", "ldb_di1_sel", base + 0x74, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) hws[IMX6QDL_CLK_LDB_DI0] = imx_clk_hw_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) hws[IMX6QDL_CLK_LDB_DI1] = imx_clk_hw_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) hws[IMX6QDL_CLK_IPU2_DI1] = imx_clk_hw_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) hws[IMX6QDL_CLK_HSI_TX] = imx_clk_hw_gate2_shared("hsi_tx", "hsi_tx_podf", base + 0x74, 16, &share_count_mipi_core_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) hws[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_hw_gate2_shared("mipi_core_cfg", "video_27m", base + 0x74, 16, &share_count_mipi_core_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) hws[IMX6QDL_CLK_MIPI_IPG] = imx_clk_hw_gate2_shared("mipi_ipg", "ipg", base + 0x74, 16, &share_count_mipi_core_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (clk_on_imx6dl())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) * The multiplexer and divider of the imx6q clock gpu2d get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) hws[IMX6QDL_CLK_MLB] = imx_clk_hw_gate2("mlb", "mlb_podf", base + 0x74, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) hws[IMX6QDL_CLK_MLB] = imx_clk_hw_gate2("mlb", "axi", base + 0x74, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) hws[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_hw_gate2_flags("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) hws[IMX6QDL_CLK_MMDC_CH1_AXI] = imx_clk_hw_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) hws[IMX6QDL_CLK_MMDC_P0_IPG] = imx_clk_hw_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) hws[IMX6QDL_CLK_OCRAM] = imx_clk_hw_gate2("ocram", "ahb", base + 0x74, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) hws[IMX6QDL_CLK_OPENVG_AXI] = imx_clk_hw_gate2("openvg_axi", "axi", base + 0x74, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) hws[IMX6QDL_CLK_PCIE_AXI] = imx_clk_hw_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) hws[IMX6QDL_CLK_PER1_BCH] = imx_clk_hw_gate2("per1_bch", "usdhc3", base + 0x78, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) hws[IMX6QDL_CLK_PWM1] = imx_clk_hw_gate2("pwm1", "ipg_per", base + 0x78, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) hws[IMX6QDL_CLK_PWM2] = imx_clk_hw_gate2("pwm2", "ipg_per", base + 0x78, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) hws[IMX6QDL_CLK_PWM3] = imx_clk_hw_gate2("pwm3", "ipg_per", base + 0x78, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) hws[IMX6QDL_CLK_PWM4] = imx_clk_hw_gate2("pwm4", "ipg_per", base + 0x78, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) hws[IMX6QDL_CLK_GPMI_BCH_APB] = imx_clk_hw_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) hws[IMX6QDL_CLK_GPMI_BCH] = imx_clk_hw_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) hws[IMX6QDL_CLK_GPMI_IO] = imx_clk_hw_gate2("gpmi_io", "enfc", base + 0x78, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) hws[IMX6QDL_CLK_GPMI_APB] = imx_clk_hw_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) hws[IMX6QDL_CLK_ROM] = imx_clk_hw_gate2_flags("rom", "ahb", base + 0x7c, 0, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) hws[IMX6QDL_CLK_SATA] = imx_clk_hw_gate2("sata", "ahb", base + 0x7c, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) hws[IMX6QDL_CLK_SDMA] = imx_clk_hw_gate2("sdma", "ahb", base + 0x7c, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) hws[IMX6QDL_CLK_SPBA] = imx_clk_hw_gate2("spba", "ipg", base + 0x7c, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) hws[IMX6QDL_CLK_SPDIF] = imx_clk_hw_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_spdif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) hws[IMX6QDL_CLK_SPDIF_GCLK] = imx_clk_hw_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) hws[IMX6QDL_CLK_SSI1_IPG] = imx_clk_hw_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) hws[IMX6QDL_CLK_SSI2_IPG] = imx_clk_hw_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) hws[IMX6QDL_CLK_SSI3_IPG] = imx_clk_hw_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) hws[IMX6QDL_CLK_SSI1] = imx_clk_hw_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) hws[IMX6QDL_CLK_SSI2] = imx_clk_hw_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) hws[IMX6QDL_CLK_SSI3] = imx_clk_hw_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) hws[IMX6QDL_CLK_UART_IPG] = imx_clk_hw_gate2("uart_ipg", "ipg", base + 0x7c, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) hws[IMX6QDL_CLK_UART_SERIAL] = imx_clk_hw_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) hws[IMX6QDL_CLK_USBOH3] = imx_clk_hw_gate2("usboh3", "ipg", base + 0x80, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) hws[IMX6QDL_CLK_USDHC1] = imx_clk_hw_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) hws[IMX6QDL_CLK_USDHC2] = imx_clk_hw_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) hws[IMX6QDL_CLK_USDHC3] = imx_clk_hw_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) hws[IMX6QDL_CLK_USDHC4] = imx_clk_hw_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) hws[IMX6QDL_CLK_EIM_SLOW] = imx_clk_hw_gate2("eim_slow", "eim_slow_podf", base + 0x80, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) hws[IMX6QDL_CLK_VDO_AXI] = imx_clk_hw_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) hws[IMX6QDL_CLK_VPU_AXI] = imx_clk_hw_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (clk_on_imx6qp()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) hws[IMX6QDL_CLK_PRE0] = imx_clk_hw_gate2("pre0", "pre_axi", base + 0x80, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) hws[IMX6QDL_CLK_PRE1] = imx_clk_hw_gate2("pre1", "pre_axi", base + 0x80, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) hws[IMX6QDL_CLK_PRE2] = imx_clk_hw_gate2("pre2", "pre_axi", base + 0x80, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) hws[IMX6QDL_CLK_PRE3] = imx_clk_hw_gate2("pre3", "pre_axi", base + 0x80, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) hws[IMX6QDL_CLK_PRG0_AXI] = imx_clk_hw_gate2_shared("prg0_axi", "ipu1_podf", base + 0x80, 24, &share_count_prg0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) hws[IMX6QDL_CLK_PRG1_AXI] = imx_clk_hw_gate2_shared("prg1_axi", "ipu2_podf", base + 0x80, 26, &share_count_prg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) hws[IMX6QDL_CLK_PRG0_APB] = imx_clk_hw_gate2_shared("prg0_apb", "ipg", base + 0x80, 24, &share_count_prg0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) hws[IMX6QDL_CLK_PRG1_APB] = imx_clk_hw_gate2_shared("prg1_apb", "ipg", base + 0x80, 26, &share_count_prg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) hws[IMX6QDL_CLK_CKO1] = imx_clk_hw_gate("cko1", "cko1_podf", base + 0x60, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) hws[IMX6QDL_CLK_CKO2] = imx_clk_hw_gate("cko2", "cko2_podf", base + 0x60, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * The gpt_3m clock is not available on i.MX6Q TO1.0. Let's point it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * to clock gpt_ipg_per to ease the gpt driver code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) hws[IMX6QDL_CLK_GPT_3M] = hws[IMX6QDL_CLK_GPT_IPG_PER];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) imx_check_clk_hws(hws, IMX6QDL_CLK_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) clk_hw_register_clkdev(hws[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) clk_set_rate(hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk, 540000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (clk_on_imx6dl())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) clk_set_parent(hws[IMX6QDL_CLK_IPU1_SEL]->clk, hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI1_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI1_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI0_SEL]->clk, hws[IMX6QDL_CLK_IPU1_DI0_PRE]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI1_SEL]->clk, hws[IMX6QDL_CLK_IPU1_DI1_PRE]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI0_SEL]->clk, hws[IMX6QDL_CLK_IPU2_DI0_PRE]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI1_SEL]->clk, hws[IMX6QDL_CLK_IPU2_DI1_PRE]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * The gpmi needs 100MHz frequency in the EDO/Sync mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * We can not get the 100MHz from the pll2_pfd0_352m.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) * So choose pll2_pfd2_396m as enfc_sel's parent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) clk_set_parent(hws[IMX6QDL_CLK_ENFC_SEL]->clk, hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) clk_prepare_enable(hws[IMX6QDL_CLK_USBPHY1_GATE]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) clk_prepare_enable(hws[IMX6QDL_CLK_USBPHY2_GATE]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * Let's initially set up CLKO with OSC24M, since this configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) * is widely used by imx6q board designs to clock audio codec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) ret = clk_set_parent(hws[IMX6QDL_CLK_CKO2_SEL]->clk, hws[IMX6QDL_CLK_OSC]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) ret = clk_set_parent(hws[IMX6QDL_CLK_CKO]->clk, hws[IMX6QDL_CLK_CKO2]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) pr_warn("failed to set up CLKO: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* Audio-related clocks configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) clk_set_parent(hws[IMX6QDL_CLK_SPDIF_SEL]->clk, hws[IMX6QDL_CLK_PLL3_PFD3_454M]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /* All existing boards with PCIe use LVDS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (IS_ENABLED(CONFIG_PCI_IMX6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) clk_set_parent(hws[IMX6QDL_CLK_LVDS1_SEL]->clk, hws[IMX6QDL_CLK_SATA_REF_100M]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) * Initialize the GPU clock muxes, so that the maximum specified clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) * rates for the respective SoC are not exceeded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (clk_on_imx6dl()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) clk_set_parent(hws[IMX6QDL_CLK_GPU3D_CORE_SEL]->clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) clk_set_parent(hws[IMX6QDL_CLK_GPU2D_CORE_SEL]->clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) } else if (clk_on_imx6q()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) clk_set_parent(hws[IMX6QDL_CLK_GPU3D_CORE_SEL]->clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) hws[IMX6QDL_CLK_MMDC_CH0_AXI]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) clk_set_parent(hws[IMX6QDL_CLK_GPU3D_SHADER_SEL]->clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) clk_set_parent(hws[IMX6QDL_CLK_GPU2D_CORE_SEL]->clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) imx_register_uart_clocks(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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