^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <soc/imx/revision.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/clock/imx5-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MX51_DPLL1_BASE 0x83f80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MX51_DPLL2_BASE 0x83f84000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MX51_DPLL3_BASE 0x83f88000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MX53_DPLL1_BASE 0x63f80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MX53_DPLL2_BASE 0x63f84000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MX53_DPLL3_BASE 0x63f88000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MX53_DPLL4_BASE 0x63f8c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MXC_CCM_CCR (ccm_base + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MXC_CCM_CCDR (ccm_base + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MXC_CCM_CSR (ccm_base + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MXC_CCM_CCSR (ccm_base + 0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MXC_CCM_CACRR (ccm_base + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MXC_CCM_CBCDR (ccm_base + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MXC_CCM_CBCMR (ccm_base + 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MXC_CCM_CSCMR1 (ccm_base + 0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MXC_CCM_CSCMR2 (ccm_base + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MXC_CCM_CSCDR1 (ccm_base + 0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MXC_CCM_CS1CDR (ccm_base + 0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MXC_CCM_CS2CDR (ccm_base + 0x2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MXC_CCM_CDCDR (ccm_base + 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MXC_CCM_CHSCDR (ccm_base + 0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MXC_CCM_CSCDR2 (ccm_base + 0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MXC_CCM_CSCDR3 (ccm_base + 0x3c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MXC_CCM_CSCDR4 (ccm_base + 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MXC_CCM_CWDR (ccm_base + 0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MXC_CCM_CDHIPR (ccm_base + 0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MXC_CCM_CDCR (ccm_base + 0x4c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MXC_CCM_CTOR (ccm_base + 0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MXC_CCM_CLPCR (ccm_base + 0x54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MXC_CCM_CISR (ccm_base + 0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MXC_CCM_CIMR (ccm_base + 0x5c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MXC_CCM_CCOSR (ccm_base + 0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MXC_CCM_CGPR (ccm_base + 0x64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MXC_CCM_CCGR0 (ccm_base + 0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MXC_CCM_CCGR1 (ccm_base + 0x6c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MXC_CCM_CCGR2 (ccm_base + 0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MXC_CCM_CCGR3 (ccm_base + 0x74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MXC_CCM_CCGR4 (ccm_base + 0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MXC_CCM_CCGR5 (ccm_base + 0x7c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MXC_CCM_CCGR6 (ccm_base + 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MXC_CCM_CCGR7 (ccm_base + 0x84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Low-power Audio Playback Mode clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static const char *lp_apm_sel[] = { "osc", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* This is used multiple times */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static const char *standard_pll_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "lp_apm", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static const char *periph_apm_sel[] = { "pll1_sw", "pll3_sw", "lp_apm", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static const char *main_bus_sel[] = { "pll2_sw", "periph_apm", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const char *per_lp_apm_sel[] = { "main_bus", "lp_apm", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static const char *per_root_sel[] = { "per_podf", "ipg", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static const char *esdhc_c_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static const char *esdhc_d_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static const char *ssi_apm_sels[] = { "ckih1", "lp_amp", "ckih2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static const char *ssi_clk_sels[] = { "pll1_sw", "pll2_sw", "pll3_sw", "ssi_apm", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static const char *ssi3_clk_sels[] = { "ssi1_root_gate", "ssi2_root_gate", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static const char *ssi_ext1_com_sels[] = { "ssi_ext1_podf", "ssi1_root_gate", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const char *emi_slow_sel[] = { "main_bus", "ahb", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static const char *mx51_tve_sel[] = { "tve_pred", "tve_ext_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static const char *gpu3d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static const char *gpu2d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const char *mx53_cko1_sel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) "cpu_podf", "pll1_sw", "pll2_sw", "pll3_sw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) "emi_slow_podf", "pll4_sw", "nfc_podf", "dummy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "di_pred", "dummy", "dummy", "ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) "ipg", "per_root", "ckil", "dummy",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const char *mx53_cko2_sel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "dummy"/* dptc_core */, "dummy"/* dptc_perich */,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "dummy", "esdhc_a_podf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "usboh3_podf", "dummy"/* wrck_clk_root */,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) "ecspi_podf", "dummy"/* pll1_ref_clk */,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) "esdhc_b_podf", "dummy"/* ddr_clk_root */,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) "dummy"/* arm_axi_clk_root */, "dummy"/* usb_phy_out */,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "vpu_sel", "ipu_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) "osc", "ckih1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "dummy", "esdhc_c_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "ssi1_root_podf", "ssi2_root_podf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) "dummy", "dummy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) "dummy"/* lpsr_clk_root */, "dummy"/* pgc_clk_root */,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) "dummy"/* tve_out */, "usb_phy_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) "tve_sel", "lp_apm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "uart_root", "dummy"/* spdif0_clk_root */,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) "dummy", "dummy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const char *mx51_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const char *mx53_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", "pll4_sw", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const char *step_sels[] = { "lp_apm", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const char *cpu_podf_sels[] = { "pll1_sw", "step_sel" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const char *ieee1588_sels[] = { "pll3_sw", "pll4_sw", "dummy" /* usbphy2_clk */, "dummy" /* fec_phy_clk */ };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static struct clk *clk[IMX5_CLK_END];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static struct clk_onecell_data clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void __init mx5_clocks_common_init(void __iomem *ccm_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) clk[IMX5_CLK_PER_LP_APM] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) clk[IMX5_CLK_PER_PRED1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) clk[IMX5_CLK_PER_PRED2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) clk[IMX5_CLK_PER_PODF] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) clk[IMX5_CLK_PER_ROOT] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) per_root_sel, ARRAY_SIZE(per_root_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) clk[IMX5_CLK_AHB] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) clk[IMX5_CLK_AHB_MAX] = imx_clk_gate2_flags("ahb_max", "ahb", MXC_CCM_CCGR0, 28, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) clk[IMX5_CLK_AIPS_TZ1] = imx_clk_gate2_flags("aips_tz1", "ahb", MXC_CCM_CCGR0, 24, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) clk[IMX5_CLK_AIPS_TZ2] = imx_clk_gate2_flags("aips_tz2", "ahb", MXC_CCM_CCGR0, 26, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) clk[IMX5_CLK_TMAX1] = imx_clk_gate2_flags("tmax1", "ahb", MXC_CCM_CCGR1, 0, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) clk[IMX5_CLK_TMAX2] = imx_clk_gate2_flags("tmax2", "ahb", MXC_CCM_CCGR1, 2, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) clk[IMX5_CLK_TMAX3] = imx_clk_gate2_flags("tmax3", "ahb", MXC_CCM_CCGR1, 4, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) clk[IMX5_CLK_SPBA] = imx_clk_gate2_flags("spba", "ipg", MXC_CCM_CCGR5, 0, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) clk[IMX5_CLK_IPG] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) clk[IMX5_CLK_AXI_A] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) clk[IMX5_CLK_AXI_B] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) clk[IMX5_CLK_UART_SEL] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) clk[IMX5_CLK_UART_PRED] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) clk[IMX5_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) clk[IMX5_CLK_ESDHC_A_PRED] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) clk[IMX5_CLK_ESDHC_A_PODF] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) clk[IMX5_CLK_ESDHC_B_PRED] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) clk[IMX5_CLK_ESDHC_B_PODF] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) clk[IMX5_CLK_EMI_SEL] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) clk[IMX5_CLK_EMI_SLOW_PODF] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) clk[IMX5_CLK_NFC_PODF] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) clk[IMX5_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) clk[IMX5_CLK_ECSPI_PRED] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) clk[IMX5_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) clk[IMX5_CLK_USBOH3_SEL] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) clk[IMX5_CLK_USBOH3_PRED] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) clk[IMX5_CLK_USBOH3_PODF] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) clk[IMX5_CLK_USB_PHY_PRED] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) clk[IMX5_CLK_USB_PHY_PODF] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) clk[IMX5_CLK_USB_PHY_SEL] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) clk[IMX5_CLK_STEP_SEL] = imx_clk_mux("step_sel", MXC_CCM_CCSR, 7, 2, step_sels, ARRAY_SIZE(step_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) clk[IMX5_CLK_CPU_PODF_SEL] = imx_clk_mux("cpu_podf_sel", MXC_CCM_CCSR, 2, 1, cpu_podf_sels, ARRAY_SIZE(cpu_podf_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) clk[IMX5_CLK_CPU_PODF] = imx_clk_divider("cpu_podf", "cpu_podf_sel", MXC_CCM_CACRR, 0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) clk[IMX5_CLK_DI_PRED] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) clk[IMX5_CLK_IIM_GATE] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) clk[IMX5_CLK_UART1_IPG_GATE] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) clk[IMX5_CLK_UART1_PER_GATE] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) clk[IMX5_CLK_UART2_IPG_GATE] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) clk[IMX5_CLK_UART2_PER_GATE] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) clk[IMX5_CLK_UART3_IPG_GATE] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) clk[IMX5_CLK_UART3_PER_GATE] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) clk[IMX5_CLK_I2C1_GATE] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) clk[IMX5_CLK_I2C2_GATE] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) clk[IMX5_CLK_PWM1_IPG_GATE] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) clk[IMX5_CLK_PWM1_HF_GATE] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) clk[IMX5_CLK_PWM2_IPG_GATE] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) clk[IMX5_CLK_PWM2_HF_GATE] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) clk[IMX5_CLK_GPT_IPG_GATE] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) clk[IMX5_CLK_GPT_HF_GATE] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) clk[IMX5_CLK_FEC_GATE] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) clk[IMX5_CLK_USBOH3_GATE] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) clk[IMX5_CLK_USBOH3_PER_GATE] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) clk[IMX5_CLK_ESDHC1_IPG_GATE] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) clk[IMX5_CLK_ESDHC2_IPG_GATE] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) clk[IMX5_CLK_ESDHC3_IPG_GATE] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) clk[IMX5_CLK_ESDHC4_IPG_GATE] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) clk[IMX5_CLK_SSI1_IPG_GATE] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) clk[IMX5_CLK_SSI2_IPG_GATE] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) clk[IMX5_CLK_SSI3_IPG_GATE] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) clk[IMX5_CLK_ECSPI1_IPG_GATE] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) clk[IMX5_CLK_ECSPI1_PER_GATE] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) clk[IMX5_CLK_ECSPI2_IPG_GATE] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) clk[IMX5_CLK_ECSPI2_PER_GATE] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) clk[IMX5_CLK_CSPI_IPG_GATE] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) clk[IMX5_CLK_SDMA_GATE] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) clk[IMX5_CLK_EMI_FAST_GATE] = imx_clk_gate2_flags("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) clk[IMX5_CLK_EMI_SLOW_GATE] = imx_clk_gate2_flags("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) clk[IMX5_CLK_IPU_SEL] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) clk[IMX5_CLK_IPU_GATE] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) clk[IMX5_CLK_NFC_GATE] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) clk[IMX5_CLK_IPU_DI0_GATE] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) clk[IMX5_CLK_IPU_DI1_GATE] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) clk[IMX5_CLK_GPU3D_SEL] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) clk[IMX5_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) clk[IMX5_CLK_GPU3D_GATE] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) clk[IMX5_CLK_GARB_GATE] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) clk[IMX5_CLK_GPU2D_GATE] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) clk[IMX5_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) clk[IMX5_CLK_VPU_GATE] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) clk[IMX5_CLK_VPU_REFERENCE_GATE] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) clk[IMX5_CLK_GPC_DVFS] = imx_clk_gate2_flags("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) clk[IMX5_CLK_SSI_APM] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) clk[IMX5_CLK_SSI1_ROOT_SEL] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) clk[IMX5_CLK_SSI2_ROOT_SEL] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) clk[IMX5_CLK_SSI3_ROOT_SEL] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) clk[IMX5_CLK_SSI_EXT1_SEL] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) clk[IMX5_CLK_SSI_EXT2_SEL] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) clk[IMX5_CLK_SSI_EXT1_COM_SEL] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) clk[IMX5_CLK_SSI_EXT2_COM_SEL] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) clk[IMX5_CLK_SSI1_ROOT_PRED] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) clk[IMX5_CLK_SSI1_ROOT_PODF] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) clk[IMX5_CLK_SSI2_ROOT_PRED] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) clk[IMX5_CLK_SSI2_ROOT_PODF] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) clk[IMX5_CLK_SSI_EXT1_PRED] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) clk[IMX5_CLK_SSI_EXT1_PODF] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) clk[IMX5_CLK_SSI_EXT2_PRED] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) clk[IMX5_CLK_SSI_EXT2_PODF] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) clk[IMX5_CLK_SSI1_ROOT_GATE] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) clk[IMX5_CLK_SSI2_ROOT_GATE] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) clk[IMX5_CLK_SSI3_ROOT_GATE] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) clk[IMX5_CLK_SSI_EXT1_GATE] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) clk[IMX5_CLK_SSI_EXT2_GATE] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) clk[IMX5_CLK_EPIT1_IPG_GATE] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) clk[IMX5_CLK_EPIT1_HF_GATE] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) clk[IMX5_CLK_EPIT2_IPG_GATE] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) clk[IMX5_CLK_EPIT2_HF_GATE] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) clk[IMX5_CLK_OWIRE_GATE] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) clk[IMX5_CLK_SRTC_GATE] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) clk[IMX5_CLK_PATA_GATE] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) clk[IMX5_CLK_SPDIF0_SEL] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) clk[IMX5_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) clk[IMX5_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) clk[IMX5_CLK_SPDIF0_COM_SEL] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) clk[IMX5_CLK_SPDIF0_GATE] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) clk[IMX5_CLK_SPDIF_IPG_GATE] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) clk[IMX5_CLK_SAHARA_IPG_GATE] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) clk[IMX5_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* move usb phy clk to 24MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static void __init mx50_clocks_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) void __iomem *ccm_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) void __iomem *pll_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) unsigned long r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) WARN_ON(!pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) WARN_ON(!pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) WARN_ON(!pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ccm_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) WARN_ON(!ccm_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) mx5_clocks_common_init(ccm_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * This clock is called periph_clk in the i.MX50 Reference Manual, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * it comes closest in scope to the main_bus_clk of i.MX51 and i.MX53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) clk[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) clk[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 21, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) clk[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) clk[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 20, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) clk[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) clk[IMX5_CLK_UART4_IPG_GATE] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) clk[IMX5_CLK_UART4_PER_GATE] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) clk[IMX5_CLK_UART5_IPG_GATE] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) clk[IMX5_CLK_UART5_PER_GATE] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) clk[IMX5_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) clk[IMX5_CLK_CKO1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) clk[IMX5_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) imx_check_clocks(clk, ARRAY_SIZE(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) clk_data.clks = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) clk_data.clk_num = ARRAY_SIZE(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Set SDHC parents to be PLL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* set SDHC root clock to 200MHZ*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) imx_print_silicon_rev("i.MX50", IMX_CHIP_REVISION_1_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) imx_register_uart_clocks(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static void __init mx51_clocks_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) void __iomem *ccm_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) void __iomem *pll_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) pll_base = ioremap(MX51_DPLL1_BASE, SZ_16K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) WARN_ON(!pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) pll_base = ioremap(MX51_DPLL2_BASE, SZ_16K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) WARN_ON(!pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) pll_base = ioremap(MX51_DPLL3_BASE, SZ_16K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) WARN_ON(!pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ccm_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) WARN_ON(!ccm_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) mx5_clocks_common_init(ccm_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) clk[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) main_bus_sel, ARRAY_SIZE(main_bus_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux_flags("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux_flags("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) clk[IMX5_CLK_TVE_SEL] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) clk[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) clk[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) clk[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) clk[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) clk[IMX5_CLK_USB_PHY_GATE] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) clk[IMX5_CLK_HSI2C_GATE] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) clk[IMX5_CLK_SCC2_IPG_GATE] = imx_clk_gate2("scc2_gate", "ipg", MXC_CCM_CCGR1, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) clk[IMX5_CLK_MIPI_HSC1_GATE] = imx_clk_gate2_flags("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) clk[IMX5_CLK_MIPI_HSC2_GATE] = imx_clk_gate2_flags("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) clk[IMX5_CLK_MIPI_ESC_GATE] = imx_clk_gate2_flags("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) clk[IMX5_CLK_MIPI_HSP_GATE] = imx_clk_gate2_flags("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) clk[IMX5_CLK_SPDIF1_SEL] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) spdif_sel, ARRAY_SIZE(spdif_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) clk[IMX5_CLK_SPDIF1_PRED] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) clk[IMX5_CLK_SPDIF1_PODF] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) clk[IMX5_CLK_SPDIF1_COM_SEL] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) clk[IMX5_CLK_SPDIF1_GATE] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) imx_check_clocks(clk, ARRAY_SIZE(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) clk_data.clks = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) clk_data.clk_num = ARRAY_SIZE(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* set the usboh3 parent to pll2_sw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Set SDHC parents to be PLL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* set SDHC root clock to 166.25MHZ*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) imx_print_silicon_rev("i.MX51", mx51_revision());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * longer supported. Set to one for better power saving.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * The effect of not setting these bits is that MIPI clocks can't be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * enabled without the IPU clock being enabled aswell.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) val = readl(MXC_CCM_CCDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) val |= 1 << 18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) writel(val, MXC_CCM_CCDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) val = readl(MXC_CCM_CLPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) val |= 1 << 23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) writel(val, MXC_CCM_CLPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) imx_register_uart_clocks(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static void __init mx53_clocks_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) void __iomem *ccm_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) void __iomem *pll_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) unsigned long r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) WARN_ON(!pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) WARN_ON(!pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) WARN_ON(!pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) pll_base = ioremap(MX53_DPLL4_BASE, SZ_16K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) WARN_ON(!pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) clk[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ccm_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) WARN_ON(!ccm_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) mx5_clocks_common_init(ccm_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) clk[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) main_bus_sel, ARRAY_SIZE(main_bus_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) clk[IMX5_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) clk[IMX5_CLK_LDB_DI1_DIV] = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) clk[IMX5_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) clk[IMX5_CLK_DI_PLL4_PODF] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) clk[IMX5_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) clk[IMX5_CLK_LDB_DI0_DIV] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) clk[IMX5_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) clk[IMX5_CLK_LDB_DI0_GATE] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) clk[IMX5_CLK_LDB_DI1_GATE] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux_flags("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux_flags("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) clk[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) clk[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) clk[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) clk[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) clk[IMX5_CLK_CAN_SEL] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) clk[IMX5_CLK_CAN1_SERIAL_GATE] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) clk[IMX5_CLK_CAN1_IPG_GATE] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) clk[IMX5_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) clk[IMX5_CLK_CAN2_SERIAL_GATE] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) clk[IMX5_CLK_CAN2_IPG_GATE] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) clk[IMX5_CLK_SATA_GATE] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) clk[IMX5_CLK_FIRI_SEL] = imx_clk_mux("firi_sel", MXC_CCM_CSCMR2, 12, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) clk[IMX5_CLK_FIRI_PRED] = imx_clk_divider("firi_pred", "firi_sel", MXC_CCM_CSCDR3, 6, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) clk[IMX5_CLK_FIRI_PODF] = imx_clk_divider("firi_podf", "firi_pred", MXC_CCM_CSCDR3, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) clk[IMX5_CLK_FIRI_SERIAL_GATE] = imx_clk_gate2("firi_serial_gate", "firi_podf", MXC_CCM_CCGR1, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) clk[IMX5_CLK_FIRI_IPG_GATE] = imx_clk_gate2("firi_ipg_gate", "ipg", MXC_CCM_CCGR1, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) clk[IMX5_CLK_CSI0_MCLK1_SEL] = imx_clk_mux("csi0_mclk1_sel", MXC_CCM_CSCMR2, 22, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) clk[IMX5_CLK_CSI0_MCLK1_PRED] = imx_clk_divider("csi0_mclk1_pred", "csi0_mclk1_sel", MXC_CCM_CSCDR4, 6, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) clk[IMX5_CLK_CSI0_MCLK1_PODF] = imx_clk_divider("csi0_mclk1_podf", "csi0_mclk1_pred", MXC_CCM_CSCDR4, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) clk[IMX5_CLK_CSI0_MCLK1_GATE] = imx_clk_gate2("csi0_mclk1_serial_gate", "csi0_mclk1_podf", MXC_CCM_CCGR6, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) clk[IMX5_CLK_IEEE1588_SEL] = imx_clk_mux("ieee1588_sel", MXC_CCM_CSCMR2, 14, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ieee1588_sels, ARRAY_SIZE(ieee1588_sels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) clk[IMX5_CLK_IEEE1588_PRED] = imx_clk_divider("ieee1588_pred", "ieee1588_sel", MXC_CCM_CSCDR2, 6, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) clk[IMX5_CLK_IEEE1588_PODF] = imx_clk_divider("ieee1588_podf", "ieee1588_pred", MXC_CCM_CSCDR2, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) clk[IMX5_CLK_IEEE1588_GATE] = imx_clk_gate2("ieee1588_serial_gate", "ieee1588_podf", MXC_CCM_CCGR7, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) clk[IMX5_CLK_UART4_IPG_GATE] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) clk[IMX5_CLK_UART4_PER_GATE] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) clk[IMX5_CLK_UART5_IPG_GATE] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) clk[IMX5_CLK_UART5_PER_GATE] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) clk[IMX5_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) clk[IMX5_CLK_CKO1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) clk[IMX5_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) clk[IMX5_CLK_ARM] = imx_clk_cpu("arm", "cpu_podf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) clk[IMX5_CLK_CPU_PODF],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) clk[IMX5_CLK_CPU_PODF_SEL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) clk[IMX5_CLK_PLL1_SW],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) clk[IMX5_CLK_STEP_SEL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) imx_check_clocks(clk, ARRAY_SIZE(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) clk_data.clks = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) clk_data.clk_num = ARRAY_SIZE(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* Set SDHC parents to be PLL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* set SDHC root clock to 200MHZ*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* move can bus clk to 24MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* make sure step clock is running from 24MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) clk_set_parent(clk[IMX5_CLK_STEP_SEL], clk[IMX5_CLK_LP_APM]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) imx_print_silicon_rev("i.MX53", mx53_revision());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) imx_register_uart_clocks(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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