Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <soc/imx/revision.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <soc/imx/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define MX35_CCM_BASE_ADDR	0x53f80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define MX35_GPT1_BASE_ADDR	0x53f90000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define MX35_INT_GPT		(NR_IRQS_LEGACY + 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define MXC_CCM_PDR0		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MX35_CCM_PDR2		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MX35_CCM_PDR3		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MX35_CCM_PDR4		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MX35_CCM_MPCTL		0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MX35_CCM_PPCTL		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MX35_CCM_CGR0		0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MX35_CCM_CGR1		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MX35_CCM_CGR2		0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MX35_CCM_CGR3		0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) struct arm_ahb_div {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	unsigned char arm, ahb, sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static struct arm_ahb_div clk_consumer[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	{ .arm = 1, .ahb = 4, .sel = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	{ .arm = 1, .ahb = 3, .sel = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	{ .arm = 2, .ahb = 2, .sel = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	{ .arm = 0, .ahb = 0, .sel = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	{ .arm = 0, .ahb = 0, .sel = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	{ .arm = 0, .ahb = 0, .sel = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	{ .arm = 4, .ahb = 1, .sel = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	{ .arm = 1, .ahb = 5, .sel = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	{ .arm = 1, .ahb = 8, .sel = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	{ .arm = 1, .ahb = 6, .sel = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	{ .arm = 2, .ahb = 4, .sel = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	{ .arm = 0, .ahb = 0, .sel = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	{ .arm = 0, .ahb = 0, .sel = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	{ .arm = 0, .ahb = 0, .sel = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	{ .arm = 4, .ahb = 2, .sel = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	{ .arm = 0, .ahb = 0, .sel = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static char hsp_div_532[] = { 4, 8, 3, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static char hsp_div_400[] = { 3, 6, 3, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static struct clk_onecell_data clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static const char *std_sel[] = {"ppll", "arm"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) enum mx35_clks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	/*  0 */ ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	/*  9 */ ipg, arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	/* 15 */ esdhc_sel, esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	/* 20 */ spdif_div_pre, spdif_div_post, ssi_sel, ssi1_div_pre,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	/* 24 */ ssi1_div_post, ssi2_div_pre, ssi2_div_post, usb_sel, usb_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	/* 29 */ nfc_div, asrc_gate, pata_gate, audmux_gate, can1_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	/* 34 */ can2_gate, cspi1_gate, cspi2_gate, ect_gate, edio_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	/* 39 */ emi_gate, epit1_gate, epit2_gate, esai_gate, esdhc1_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	/* 44 */ esdhc2_gate, esdhc3_gate, fec_gate, gpio1_gate, gpio2_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	/* 49 */ gpio3_gate, gpt_gate, i2c1_gate, i2c2_gate, i2c3_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	/* 54 */ iomuxc_gate, ipu_gate, kpp_gate, mlb_gate, mshc_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	/* 59 */ owire_gate, pwm_gate, rngc_gate, rtc_gate, rtic_gate, scc_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	/* 65 */ sdma_gate, spba_gate, spdif_gate, ssi1_gate, ssi2_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	/* 70 */ uart1_gate, uart2_gate, uart3_gate, usbotg_gate, wdog_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	/* 75 */ max_gate, admux_gate, csi_gate, csi_div, csi_sel, iim_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	/* 81 */ gpu2d_gate, ckil, clk_max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static struct clk *clk[clk_max];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static void __init _mx35_clocks_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	u32 pdr0, consumer_sel, hsp_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct arm_ahb_div *aad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	unsigned char *hsp_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	base = ioremap(MX35_CCM_BASE_ADDR, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	BUG_ON(!base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	pdr0 = __raw_readl(base + MXC_CCM_PDR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	consumer_sel = (pdr0 >> 16) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	aad = &clk_consumer[consumer_sel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	if (!aad->arm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		pr_err("i.MX35 clk: illegal consumer mux selection 0x%x\n", consumer_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		 * We are basically stuck. Continue with a default entry and hope we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		 * get far enough to actually show the above message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		aad = &clk_consumer[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	clk[ckih] = imx_clk_fixed("ckih", 24000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	clk[ckil] = imx_clk_fixed("ckil", 32768);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	if (aad->sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		clk[arm] = imx_clk_fixed_factor("arm", "mpll_075", 1, aad->arm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	if (clk_get_rate(clk[arm]) > 400000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		hsp_div = hsp_div_532;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		hsp_div = hsp_div_400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	hsp_sel = (pdr0 >> 20) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (!hsp_div[hsp_sel]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		pr_err("i.MX35 clk: illegal hsp clk selection 0x%x\n", hsp_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		hsp_sel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	clk[hsp] = imx_clk_fixed_factor("hsp", "arm", 1, hsp_div[hsp_sel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	clk[ahb] = imx_clk_fixed_factor("ahb", "arm", 1, aad->ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	clk[arm_per_div] = imx_clk_divider("arm_per_div", "arm", base + MX35_CCM_PDR4, 16, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	clk[ahb_per_div] = imx_clk_divider("ahb_per_div", "ahb", base + MXC_CCM_PDR0, 12, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	clk[ipg_per] = imx_clk_mux("ipg_per", base + MXC_CCM_PDR0, 26, 1, ipg_per_sel, ARRAY_SIZE(ipg_per_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	clk[uart_sel] = imx_clk_mux("uart_sel", base + MX35_CCM_PDR3, 14, 1, std_sel, ARRAY_SIZE(std_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	clk[uart_div] = imx_clk_divider("uart_div", "uart_sel", base + MX35_CCM_PDR4, 10, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	clk[esdhc_sel] = imx_clk_mux("esdhc_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	clk[esdhc1_div] = imx_clk_divider("esdhc1_div", "esdhc_sel", base + MX35_CCM_PDR3, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	clk[esdhc2_div] = imx_clk_divider("esdhc2_div", "esdhc_sel", base + MX35_CCM_PDR3, 8, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	clk[esdhc3_div] = imx_clk_divider("esdhc3_div", "esdhc_sel", base + MX35_CCM_PDR3, 16, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	clk[spdif_sel] = imx_clk_mux("spdif_sel", base + MX35_CCM_PDR3, 22, 1, std_sel, ARRAY_SIZE(std_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	clk[spdif_div_pre] = imx_clk_divider("spdif_div_pre", "spdif_sel", base + MX35_CCM_PDR3, 29, 3); /* divide by 1 not allowed */ 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	clk[spdif_div_post] = imx_clk_divider("spdif_div_post", "spdif_div_pre", base + MX35_CCM_PDR3, 23, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	clk[ssi_sel] = imx_clk_mux("ssi_sel", base + MX35_CCM_PDR2, 6, 1, std_sel, ARRAY_SIZE(std_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	clk[ssi1_div_pre] = imx_clk_divider("ssi1_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 24, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	clk[ssi1_div_post] = imx_clk_divider("ssi1_div_post", "ssi1_div_pre", base + MX35_CCM_PDR2, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	clk[ssi2_div_pre] = imx_clk_divider("ssi2_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 27, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	clk[ssi2_div_post] = imx_clk_divider("ssi2_div_post", "ssi2_div_pre", base + MX35_CCM_PDR2, 8, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	clk[usb_sel] = imx_clk_mux("usb_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	clk[usb_div] = imx_clk_divider("usb_div", "usb_sel", base + MX35_CCM_PDR4, 22, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	clk[csi_sel] = imx_clk_mux("csi_sel", base + MX35_CCM_PDR2, 7, 1, std_sel, ARRAY_SIZE(std_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MX35_CCM_PDR2, 16, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0,  0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0,  2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0,  4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	clk[can1_gate] = imx_clk_gate2("can1_gate", "ipg", base + MX35_CCM_CGR0,  6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	clk[can2_gate] = imx_clk_gate2("can2_gate", "ipg", base + MX35_CCM_CGR0,  8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MX35_CCM_CGR0, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MX35_CCM_CGR0, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	clk[ect_gate] = imx_clk_gate2("ect_gate", "ipg", base + MX35_CCM_CGR0, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	clk[edio_gate] = imx_clk_gate2("edio_gate",   "ipg", base + MX35_CCM_CGR0, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	clk[emi_gate] = imx_clk_gate2("emi_gate", "ipg", base + MX35_CCM_CGR0, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	clk[epit1_gate] = imx_clk_gate2("epit1_gate", "ipg", base + MX35_CCM_CGR0, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	clk[epit2_gate] = imx_clk_gate2("epit2_gate", "ipg", base + MX35_CCM_CGR0, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	clk[esai_gate] = imx_clk_gate2("esai_gate",   "ipg", base + MX35_CCM_CGR0, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	clk[esdhc1_gate] = imx_clk_gate2("esdhc1_gate", "esdhc1_div", base + MX35_CCM_CGR0, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	clk[esdhc2_gate] = imx_clk_gate2("esdhc2_gate", "esdhc2_div", base + MX35_CCM_CGR0, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	clk[esdhc3_gate] = imx_clk_gate2("esdhc3_gate", "esdhc3_div", base + MX35_CCM_CGR0, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", base + MX35_CCM_CGR1,  0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	clk[gpio1_gate] = imx_clk_gate2("gpio1_gate", "ipg", base + MX35_CCM_CGR1,  2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	clk[gpio2_gate] = imx_clk_gate2("gpio2_gate", "ipg", base + MX35_CCM_CGR1,  4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	clk[gpio3_gate] = imx_clk_gate2("gpio3_gate", "ipg", base + MX35_CCM_CGR1,  6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", base + MX35_CCM_CGR1,  8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "ipg_per", base + MX35_CCM_CGR1, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "ipg_per", base + MX35_CCM_CGR1, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "ipg_per", base + MX35_CCM_CGR1, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	clk[iomuxc_gate] = imx_clk_gate2("iomuxc_gate", "ipg", base + MX35_CCM_CGR1, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MX35_CCM_CGR1, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MX35_CCM_CGR1, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	clk[mlb_gate] = imx_clk_gate2("mlb_gate", "ahb", base + MX35_CCM_CGR1, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	clk[mshc_gate] = imx_clk_gate2("mshc_gate", "dummy", base + MX35_CCM_CGR1, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	clk[owire_gate] = imx_clk_gate2("owire_gate", "ipg_per", base + MX35_CCM_CGR1, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	clk[pwm_gate] = imx_clk_gate2("pwm_gate", "ipg_per", base + MX35_CCM_CGR1, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	clk[rngc_gate] = imx_clk_gate2("rngc_gate", "ipg", base + MX35_CCM_CGR1, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MX35_CCM_CGR2,  0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MX35_CCM_CGR2,  2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	clk[scc_gate] = imx_clk_gate2("scc_gate", "ipg", base + MX35_CCM_CGR2,  4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MX35_CCM_CGR2,  6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	clk[spba_gate] = imx_clk_gate2("spba_gate", "ipg", base + MX35_CCM_CGR2,  8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	clk[spdif_gate] = imx_clk_gate2("spdif_gate", "spdif_div_post", base + MX35_CCM_CGR2, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "ssi1_div_post", base + MX35_CCM_CGR2, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "ssi2_div_post", base + MX35_CCM_CGR2, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	clk[uart1_gate] = imx_clk_gate2("uart1_gate", "uart_div", base + MX35_CCM_CGR2, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	clk[uart2_gate] = imx_clk_gate2("uart2_gate", "uart_div", base + MX35_CCM_CGR2, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	clk[uart3_gate] = imx_clk_gate2("uart3_gate", "uart_div", base + MX35_CCM_CGR2, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	clk[usbotg_gate] = imx_clk_gate2("usbotg_gate", "ahb", base + MX35_CCM_CGR2, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MX35_CCM_CGR2, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MX35_CCM_CGR3,  0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3,  2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3,  4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	imx_check_clocks(clk, ARRAY_SIZE(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	clk_prepare_enable(clk[spba_gate]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	clk_prepare_enable(clk[gpio1_gate]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	clk_prepare_enable(clk[gpio2_gate]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	clk_prepare_enable(clk[gpio3_gate]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	clk_prepare_enable(clk[iim_gate]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	clk_prepare_enable(clk[emi_gate]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	clk_prepare_enable(clk[max_gate]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	clk_prepare_enable(clk[iomuxc_gate]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	 * SCC is needed to boot via mmc after a watchdog reset. The clock code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	 * before conversion to common clk also enabled UART1 (which isn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	 * handled here and not needed for mmc) and IIM (which is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	 * unconditionally above).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	clk_prepare_enable(clk[scc_gate]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	imx_register_uart_clocks(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	imx_print_silicon_rev("i.MX35", mx35_revision());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static void __init mx35_clocks_init_dt(struct device_node *ccm_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	_mx35_clocks_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	clk_data.clks = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	clk_data.clk_num = ARRAY_SIZE(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	of_clk_add_provider(ccm_node, of_clk_src_onecell_get, &clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) CLK_OF_DECLARE(imx35, "fsl,imx35-ccm", mx35_clocks_init_dt);