^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <dt-bindings/clock/imx27-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <soc/imx/revision.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <soc/imx/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MX27_CCM_BASE_ADDR 0x10027000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MX27_GPT1_BASE_ADDR 0x10003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MX27_INT_GPT1 (NR_IRQS_LEGACY + 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static void __iomem *ccm __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CCM_CSCR (ccm + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CCM_MPCTL0 (ccm + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CCM_MPCTL1 (ccm + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CCM_SPCTL0 (ccm + 0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CCM_SPCTL1 (ccm + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CCM_PCDR0 (ccm + 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CCM_PCDR1 (ccm + 0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CCM_PCCR0 (ccm + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CCM_PCCR1 (ccm + 0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CCM_CCSR (ccm + 0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const char *vpu_sel_clks[] = { "spll", "mpll_main2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static const char *mpll_sel_clks[] = { "fpm", "mpll_osc_sel", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static const char *mpll_osc_sel_clks[] = { "ckih_gate", "ckih_div1p5", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static const char *clko_sel_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) "ckil", "fpm", "ckih_gate", "ckih_gate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) "ckih_gate", "mpll", "spll", "cpu_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) "ahb", "ipg", "per1_div", "per2_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) "per3_div", "per4_div", "ssi1_div", "ssi2_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) "nfc_div", "mshc_div", "vpu_div", "60m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "32k", "usb_div", "dptc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const char *ssi_sel_clks[] = { "spll_gate", "mpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static struct clk *clk[IMX27_CLK_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static struct clk_onecell_data clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static void __init _mx27_clocks_init(unsigned long fref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) BUG_ON(!ccm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) clk[IMX27_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) clk[IMX27_CLK_CKIH] = imx_clk_fixed("ckih", fref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) clk[IMX27_CLK_CKIL] = imx_clk_fixed("ckil", 32768);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) clk[IMX27_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) clk[IMX27_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) clk[IMX27_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) clk[IMX27_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) clk[IMX27_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) clk[IMX27_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX27, "mpll", "mpll_sel", CCM_MPCTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) clk[IMX27_CLK_SPLL] = imx_clk_pllv1(IMX_PLLV1_IMX27, "spll", "ckih_gate", CCM_SPCTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) clk[IMX27_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) clk[IMX27_CLK_MPLL_MAIN2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) clk[IMX27_CLK_IPG] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) clk[IMX27_CLK_IPG] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) clk[IMX27_CLK_MSHC_DIV] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) clk[IMX27_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) clk[IMX27_CLK_PER1_DIV] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) clk[IMX27_CLK_PER2_DIV] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) clk[IMX27_CLK_PER3_DIV] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) clk[IMX27_CLK_PER4_DIV] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) clk[IMX27_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) clk[IMX27_CLK_VPU_DIV] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) clk[IMX27_CLK_USB_DIV] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) clk[IMX27_CLK_CPU_SEL] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) clk[IMX27_CLK_CLKO_SEL] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) clk[IMX27_CLK_CPU_DIV] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) clk[IMX27_CLK_CPU_DIV] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) clk[IMX27_CLK_CLKO_DIV] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) clk[IMX27_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) clk[IMX27_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) clk[IMX27_CLK_SSI1_DIV] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) clk[IMX27_CLK_SSI2_DIV] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) clk[IMX27_CLK_CLKO_EN] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) clk[IMX27_CLK_SSI2_IPG_GATE] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) clk[IMX27_CLK_SSI1_IPG_GATE] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) clk[IMX27_CLK_SLCDC_IPG_GATE] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) clk[IMX27_CLK_SDHC3_IPG_GATE] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) clk[IMX27_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) clk[IMX27_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) clk[IMX27_CLK_SCC_IPG_GATE] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) clk[IMX27_CLK_SAHARA_IPG_GATE] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) clk[IMX27_CLK_RTIC_IPG_GATE] = imx_clk_gate("rtic_ipg_gate", "ipg", CCM_PCCR0, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) clk[IMX27_CLK_RTC_IPG_GATE] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) clk[IMX27_CLK_PWM_IPG_GATE] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) clk[IMX27_CLK_OWIRE_IPG_GATE] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) clk[IMX27_CLK_MSHC_IPG_GATE] = imx_clk_gate("mshc_ipg_gate", "ipg", CCM_PCCR0, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) clk[IMX27_CLK_LCDC_IPG_GATE] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) clk[IMX27_CLK_KPP_IPG_GATE] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) clk[IMX27_CLK_IIM_IPG_GATE] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) clk[IMX27_CLK_I2C2_IPG_GATE] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) clk[IMX27_CLK_I2C1_IPG_GATE] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) clk[IMX27_CLK_GPT6_IPG_GATE] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) clk[IMX27_CLK_GPT5_IPG_GATE] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) clk[IMX27_CLK_GPT4_IPG_GATE] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) clk[IMX27_CLK_GPT3_IPG_GATE] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) clk[IMX27_CLK_GPT2_IPG_GATE] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) clk[IMX27_CLK_GPT1_IPG_GATE] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) clk[IMX27_CLK_GPIO_IPG_GATE] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) clk[IMX27_CLK_FEC_IPG_GATE] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) clk[IMX27_CLK_EMMA_IPG_GATE] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) clk[IMX27_CLK_DMA_IPG_GATE] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) clk[IMX27_CLK_CSPI3_IPG_GATE] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) clk[IMX27_CLK_CSPI2_IPG_GATE] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) clk[IMX27_CLK_CSPI1_IPG_GATE] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) clk[IMX27_CLK_MSHC_BAUD_GATE] = imx_clk_gate("mshc_baud_gate", "mshc_div", CCM_PCCR1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) clk[IMX27_CLK_NFC_BAUD_GATE] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) clk[IMX27_CLK_SSI2_BAUD_GATE] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) clk[IMX27_CLK_SSI1_BAUD_GATE] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) clk[IMX27_CLK_VPU_BAUD_GATE] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) clk[IMX27_CLK_PER4_GATE] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) clk[IMX27_CLK_PER3_GATE] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) clk[IMX27_CLK_PER2_GATE] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) clk[IMX27_CLK_PER1_GATE] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) clk[IMX27_CLK_USB_AHB_GATE] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) clk[IMX27_CLK_SLCDC_AHB_GATE] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) clk[IMX27_CLK_SAHARA_AHB_GATE] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) clk[IMX27_CLK_RTIC_AHB_GATE] = imx_clk_gate("rtic_ahb_gate", "ahb", CCM_PCCR1, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) clk[IMX27_CLK_LCDC_AHB_GATE] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) clk[IMX27_CLK_VPU_AHB_GATE] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) clk[IMX27_CLK_FEC_AHB_GATE] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) clk[IMX27_CLK_EMMA_AHB_GATE] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) clk[IMX27_CLK_EMI_AHB_GATE] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) clk[IMX27_CLK_DMA_AHB_GATE] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) clk[IMX27_CLK_CSI_AHB_GATE] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) clk[IMX27_CLK_BROM_AHB_GATE] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) clk[IMX27_CLK_ATA_AHB_GATE] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) clk[IMX27_CLK_WDOG_IPG_GATE] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) clk[IMX27_CLK_USB_IPG_GATE] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) clk[IMX27_CLK_UART6_IPG_GATE] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) clk[IMX27_CLK_UART5_IPG_GATE] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) clk[IMX27_CLK_UART4_IPG_GATE] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) clk[IMX27_CLK_UART3_IPG_GATE] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) clk[IMX27_CLK_UART2_IPG_GATE] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) clk[IMX27_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) imx_check_clocks(clk, ARRAY_SIZE(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) clk_register_clkdev(clk[IMX27_CLK_CPU_DIV], NULL, "cpu0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) imx_register_uart_clocks(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) imx_print_silicon_rev("i.MX27", mx27_revision());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static void __init mx27_clocks_init_dt(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct device_node *refnp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 fref = 26000000; /* default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) for_each_compatible_node(refnp, NULL, "fixed-clock") {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (!of_device_is_compatible(refnp, "fsl,imx-osc26m"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (!of_property_read_u32(refnp, "clock-frequency", &fref)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) of_node_put(refnp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ccm = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) _mx27_clocks_init(fref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) clk_data.clks = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) clk_data.clk_num = ARRAY_SIZE(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) CLK_OF_DECLARE(imx27_ccm, "fsl,imx27-ccm", mx27_clocks_init_dt);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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