^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/clock/imx1-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <soc/imx/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MX1_CCM_BASE_ADDR 0x0021b000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MX1_TIM1_BASE_ADDR 0x00220000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MX1_TIM1_INT (NR_IRQS_LEGACY + 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static const char *prem_sel_clks[] = { "clk32_premult", "clk16m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) "prem", "fclk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static struct clk *clk[IMX1_CLK_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static struct clk_onecell_data clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static void __iomem *ccm __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CCM_CSCR (ccm + 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CCM_MPCTL0 (ccm + 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CCM_SPCTL0 (ccm + 0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CCM_PCDR (ccm + 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SCM_GCCR (ccm + 0x0810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static void __init mx1_clocks_init_dt(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ccm = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) BUG_ON(!ccm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) clk[IMX1_CLK_CLK32] = imx_obtain_fixed_clock("clk32", 32768);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) clk[IMX1_CLK_CLK16M_EXT] = imx_clk_fixed("clk16m_ext", 16000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) clk[IMX1_CLK_CLK16M] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) clk[IMX1_CLK_CLK32_PREMULT] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) clk[IMX1_CLK_PREM] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks, ARRAY_SIZE(prem_sel_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) clk[IMX1_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX1, "mpll", "clk32_premult", CCM_MPCTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) clk[IMX1_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) clk[IMX1_CLK_SPLL] = imx_clk_pllv1(IMX_PLLV1_IMX1, "spll", "prem", CCM_SPCTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) clk[IMX1_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) clk[IMX1_CLK_MCU] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) clk[IMX1_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) clk[IMX1_CLK_HCLK] = imx_clk_divider("hclk", "spll_gate", CCM_CSCR, 10, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) clk[IMX1_CLK_CLK48M] = imx_clk_divider("clk48m", "spll_gate", CCM_CSCR, 26, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) clk[IMX1_CLK_PER1] = imx_clk_divider("per1", "spll_gate", CCM_PCDR, 0, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) clk[IMX1_CLK_PER2] = imx_clk_divider("per2", "spll_gate", CCM_PCDR, 4, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) clk[IMX1_CLK_PER3] = imx_clk_divider("per3", "spll_gate", CCM_PCDR, 16, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) clk[IMX1_CLK_CLKO] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) clk[IMX1_CLK_UART3_GATE] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) clk[IMX1_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) clk[IMX1_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) clk[IMX1_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) clk[IMX1_CLK_CSI_GATE] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) clk[IMX1_CLK_MMA_GATE] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) clk[IMX1_CLK_USBD_GATE] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) imx_check_clocks(clk, ARRAY_SIZE(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) clk_data.clks = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) clk_data.clk_num = ARRAY_SIZE(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) CLK_OF_DECLARE(imx1_ccm, "fsl,imx1-ccm", mx1_clocks_init_dt);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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