^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Gated clock implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * DOC: basic gateable clock which can gate and ungate its output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Traits of this clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * prepare - clk_(un)prepare only ensures parent is (un)prepared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * enable - clk_enable and clk_disable are functional & control gating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * rate - inherits rate from parent. No clk_set_rate support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * parent - fixed parent. No clk_set_parent support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct clk_gate2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u8 bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u8 cgr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned int *share_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define to_clk_gate2(_hw) container_of(_hw, struct clk_gate2, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static int clk_gate2_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct clk_gate2 *gate = to_clk_gate2(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) spin_lock_irqsave(gate->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (gate->share_count && (*gate->share_count)++ > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ret = clk_gate_ops.enable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) reg = readl(gate->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) reg &= ~(3 << gate->bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) reg |= gate->cgr_val << gate->bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) writel(reg, gate->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) spin_unlock_irqrestore(gate->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static void clk_gate2_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct clk_gate2 *gate = to_clk_gate2(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) spin_lock_irqsave(gate->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (gate->share_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (WARN_ON(*gate->share_count == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) else if (--(*gate->share_count) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) clk_gate_ops.disable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) reg = readl(gate->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) reg &= ~(3 << gate->bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) writel(reg, gate->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) spin_unlock_irqrestore(gate->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 val = readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (((val >> bit_idx) & 1) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int clk_gate2_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct clk_gate2 *gate = to_clk_gate2(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return clk_gate_ops.is_enabled(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void clk_gate2_disable_unused(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct clk_gate2 *gate = to_clk_gate2(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) spin_lock_irqsave(gate->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (!gate->share_count || *gate->share_count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) reg = readl(gate->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) reg &= ~(3 << gate->bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) writel(reg, gate->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) spin_unlock_irqrestore(gate->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const struct clk_ops clk_gate2_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .enable = clk_gate2_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .disable = clk_gate2_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .disable_unused = clk_gate2_disable_unused,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .is_enabled = clk_gate2_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) const char *parent_name, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) void __iomem *reg, u8 bit_idx, u8 cgr_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u8 clk_gate2_flags, spinlock_t *lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int *share_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct clk_gate2 *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) gate = kzalloc(sizeof(struct clk_gate2), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (!gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* struct clk_gate2 assignments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) gate->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) gate->bit_idx = bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) gate->cgr_val = cgr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) gate->flags = clk_gate2_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) gate->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) gate->share_count = share_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) init.ops = &clk_gate2_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) init.parent_names = parent_name ? &parent_name : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) init.num_parents = parent_name ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) gate->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) hw = &gate->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ret = clk_hw_register(dev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) kfree(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) EXPORT_SYMBOL_GPL(clk_hw_register_gate2);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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