Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2014 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * struct clk_gate_exclusive - i.MX specific gate clock which is mutually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * exclusive with other gate clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * @gate: the parent class
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * @exclusive_mask: mask of gate bits which are mutually exclusive to this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  *	gate clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  * The imx exclusive gate clock is a subclass of basic clk_gate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  * with an addtional mask to indicate which other gate bits in the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  * register is mutually exclusive to this gate clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct clk_gate_exclusive {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	struct clk_gate gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	u32 exclusive_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static int clk_gate_exclusive_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	struct clk_gate *gate = to_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	struct clk_gate_exclusive *exgate = container_of(gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 					struct clk_gate_exclusive, gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	u32 val = readl(gate->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	if (val & exgate->exclusive_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	return clk_gate_ops.enable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static void clk_gate_exclusive_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	clk_gate_ops.disable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static int clk_gate_exclusive_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	return clk_gate_ops.is_enabled(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static const struct clk_ops clk_gate_exclusive_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	.enable = clk_gate_exclusive_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	.disable = clk_gate_exclusive_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	.is_enabled = clk_gate_exclusive_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	 void __iomem *reg, u8 shift, u32 exclusive_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	struct clk_gate_exclusive *exgate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	struct clk_gate *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	if (exclusive_mask == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 		return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	exgate = kzalloc(sizeof(*exgate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	if (!exgate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 		return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	gate = &exgate->gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	init.ops = &clk_gate_exclusive_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	init.flags = CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	init.parent_names = parent ? &parent : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	init.num_parents = parent ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	gate->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 	gate->bit_idx = shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 	gate->lock = &imx_ccm_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 	gate->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 	exgate->exclusive_mask = exclusive_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 	hw = &gate->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 	ret = clk_hw_register(NULL, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 		kfree(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 		return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 	return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }