^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2018 NXP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This driver supports the fractional plls found in the imx8m SOCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Documentation for this fractional pll can be found at:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PLL_CFG0 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PLL_CFG1 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PLL_LOCK_STATUS BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PLL_PD_MASK BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PLL_BYPASS_MASK BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PLL_NEWDIV_VAL BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PLL_NEWDIV_ACK BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PLL_FRAC_DIV_MASK GENMASK(30, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PLL_INT_DIV_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PLL_OUTPUT_DIV_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PLL_FRAC_DENOM 0x1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PLL_FRAC_LOCK_TIMEOUT 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PLL_FRAC_ACK_TIMEOUT 500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct clk_frac_pll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define to_clk_frac_pll(_hw) container_of(_hw, struct clk_frac_pll, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static int clk_wait_lock(struct clk_frac_pll *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return readl_poll_timeout(pll->base, val, val & PLL_LOCK_STATUS, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PLL_FRAC_LOCK_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static int clk_wait_ack(struct clk_frac_pll *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* return directly if the pll is in powerdown or in bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (readl_relaxed(pll->base) & (PLL_PD_MASK | PLL_BYPASS_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Wait for the pll's divfi and divff to be reloaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return readl_poll_timeout(pll->base, val, val & PLL_NEWDIV_ACK, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PLL_FRAC_ACK_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int clk_pll_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct clk_frac_pll *pll = to_clk_frac_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) val = readl_relaxed(pll->base + PLL_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) val &= ~PLL_PD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) writel_relaxed(val, pll->base + PLL_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return clk_wait_lock(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static void clk_pll_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct clk_frac_pll *pll = to_clk_frac_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) val = readl_relaxed(pll->base + PLL_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) val |= PLL_PD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) writel_relaxed(val, pll->base + PLL_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int clk_pll_is_prepared(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct clk_frac_pll *pll = to_clk_frac_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) val = readl_relaxed(pll->base + PLL_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return (val & PLL_PD_MASK) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct clk_frac_pll *pll = to_clk_frac_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 val, divff, divfi, divq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u64 temp64 = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u64 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) val = readl_relaxed(pll->base + PLL_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) divq = (FIELD_GET(PLL_OUTPUT_DIV_MASK, val) + 1) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) val = readl_relaxed(pll->base + PLL_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) divff = FIELD_GET(PLL_FRAC_DIV_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) divfi = FIELD_GET(PLL_INT_DIV_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) temp64 *= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) temp64 *= divff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) do_div(temp64, PLL_FRAC_DENOM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) do_div(temp64, divq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) rate = parent_rate * 8 * (divfi + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) do_div(rate, divq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) rate += temp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u64 parent_rate = *prate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 divff, divfi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u64 temp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) parent_rate *= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) rate *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) temp64 = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) do_div(temp64, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) divfi = temp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) temp64 = rate - divfi * parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) temp64 *= PLL_FRAC_DENOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) do_div(temp64, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) divff = temp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) temp64 = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) temp64 *= divff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) do_div(temp64, PLL_FRAC_DENOM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) rate = parent_rate * divfi + temp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return rate / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * To simplify the clock calculation, we can keep the 'PLL_OUTPUT_VAL' at zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * (means the PLL output will be divided by 2). So the PLL output can use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * the below formula:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * pllout = parent_rate * 8 / 2 * DIVF_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * where DIVF_VAL = 1 + DIVFI + DIVFF / 2^24.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct clk_frac_pll *pll = to_clk_frac_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 val, divfi, divff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u64 temp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) parent_rate *= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) rate *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) divfi = rate / parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) temp64 = parent_rate * divfi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) temp64 = rate - temp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) temp64 *= PLL_FRAC_DENOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) do_div(temp64, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) divff = temp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) val = readl_relaxed(pll->base + PLL_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) val &= ~(PLL_FRAC_DIV_MASK | PLL_INT_DIV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) val |= (divff << 7) | (divfi - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) writel_relaxed(val, pll->base + PLL_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) val = readl_relaxed(pll->base + PLL_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) val &= ~0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) writel_relaxed(val, pll->base + PLL_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Set the NEV_DIV_VAL to reload the DIVFI and DIVFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) val = readl_relaxed(pll->base + PLL_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) val |= PLL_NEWDIV_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) writel_relaxed(val, pll->base + PLL_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ret = clk_wait_ack(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* clear the NEV_DIV_VAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) val = readl_relaxed(pll->base + PLL_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) val &= ~PLL_NEWDIV_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) writel_relaxed(val, pll->base + PLL_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static const struct clk_ops clk_frac_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .prepare = clk_pll_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .unprepare = clk_pll_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .is_prepared = clk_pll_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .recalc_rate = clk_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .round_rate = clk_pll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .set_rate = clk_pll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct clk_hw *imx_clk_hw_frac_pll(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct clk_frac_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) pll = kzalloc(sizeof(*pll), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (!pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) init.ops = &clk_frac_pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) pll->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) pll->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) hw = &pll->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ret = clk_hw_register(NULL, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) EXPORT_SYMBOL_GPL(imx_clk_hw_frac_pll);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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