^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 Lucas Stach <l.stach@pengutronix.de>, Pengutronix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct clk_cpu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct clk *div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct clk *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct clk *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct clk *step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static inline struct clk_cpu *to_clk_cpu(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) return container_of(hw, struct clk_cpu, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static unsigned long clk_cpu_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct clk_cpu *cpu = to_clk_cpu(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) return clk_get_rate(cpu->div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static long clk_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct clk_cpu *cpu = to_clk_cpu(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return clk_round_rate(cpu->pll, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static int clk_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct clk_cpu *cpu = to_clk_cpu(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* switch to PLL bypass clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ret = clk_set_parent(cpu->mux, cpu->step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* reprogram PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ret = clk_set_rate(cpu->pll, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) clk_set_parent(cpu->mux, cpu->pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* switch back to PLL clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) clk_set_parent(cpu->mux, cpu->pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Ensure the divider is what we expect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) clk_set_rate(cpu->div, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static const struct clk_ops clk_cpu_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .recalc_rate = clk_cpu_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .round_rate = clk_cpu_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .set_rate = clk_cpu_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct clk *div, struct clk *mux, struct clk *pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct clk *step)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct clk_cpu *cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (!cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) cpu->div = div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) cpu->mux = mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) cpu->pll = pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) cpu->step = step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) init.ops = &clk_cpu_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) init.flags = CLK_IS_CRITICAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) cpu->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) hw = &cpu->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ret = clk_hw_register(NULL, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) kfree(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) EXPORT_SYMBOL_GPL(imx_clk_hw_cpu);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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