^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2018 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PCG_PREDIV_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PCG_PREDIV_WIDTH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PCG_PREDIV_MAX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PCG_DIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PCG_CORE_DIV_WIDTH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PCG_DIV_WIDTH 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PCG_DIV_MAX 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PCG_PCS_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PCG_PCS_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PCG_CGC_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct clk_divider *divider = to_clk_divider(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned long prediv_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned int prediv_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned int div_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) prediv_value = readl(divider->reg) >> divider->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) prediv_value &= clk_div_mask(divider->width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) prediv_rate = divider_recalc_rate(hw, parent_rate, prediv_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) NULL, divider->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) divider->width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) div_value = readl(divider->reg) >> PCG_DIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) div_value &= clk_div_mask(PCG_DIV_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return divider_recalc_rate(hw, prediv_rate, div_value, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) divider->flags, PCG_DIV_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int imx8m_clk_composite_compute_dividers(unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int *prediv, int *postdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int div1, div2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int error = INT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *prediv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *postdiv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) for (div2 = 1; div2 <= PCG_DIV_MAX; div2++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int new_error = ((parent_rate / div1) / div2) - rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (abs(new_error) < abs(error)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) *prediv = div1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *postdiv = div2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) error = new_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static long imx8m_clk_composite_divider_round_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int prediv_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int div_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) imx8m_clk_composite_compute_dividers(rate, *prate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) &prediv_value, &div_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) rate = DIV_ROUND_UP(*prate, prediv_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return DIV_ROUND_UP(rate, div_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct clk_divider *divider = to_clk_divider(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int prediv_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int div_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ret = imx8m_clk_composite_compute_dividers(rate, parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) &prediv_value, &div_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) spin_lock_irqsave(divider->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) val = readl(divider->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) val &= ~((clk_div_mask(divider->width) << divider->shift) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) val |= (u32)(prediv_value - 1) << divider->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) writel(val, divider->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) spin_unlock_irqrestore(divider->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const struct clk_ops imx8m_clk_composite_divider_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .recalc_rate = imx8m_clk_composite_divider_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .round_rate = imx8m_clk_composite_divider_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .set_rate = imx8m_clk_composite_divider_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return clk_mux_ops.get_parent(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int imx8m_clk_composite_mux_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct clk_mux *mux = to_clk_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (mux->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) spin_lock_irqsave(mux->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) reg = readl(mux->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) reg &= ~(mux->mask << mux->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) val = val << mux->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) reg |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * write twice to make sure non-target interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * SEL_A/B point the same clk input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) writel(reg, mux->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) writel(reg, mux->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (mux->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) spin_unlock_irqrestore(mux->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) imx8m_clk_composite_mux_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return clk_mux_ops.determine_rate(hw, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct clk_ops imx8m_clk_composite_mux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .get_parent = imx8m_clk_composite_mux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .set_parent = imx8m_clk_composite_mux_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .determine_rate = imx8m_clk_composite_mux_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) const char * const *parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int num_parents, void __iomem *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 composite_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct clk_hw *div_hw, *gate_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct clk_divider *div = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct clk_gate *gate = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct clk_mux *mux = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) const struct clk_ops *divider_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) const struct clk_ops *mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) mux = kzalloc(sizeof(*mux), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (!mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) mux_hw = &mux->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) mux->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) mux->shift = PCG_PCS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) mux->mask = PCG_PCS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) mux->lock = &imx_ccm_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) div = kzalloc(sizeof(*div), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (!div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) div_hw = &div->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) div->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (composite_flags & IMX_COMPOSITE_CORE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) div->shift = PCG_DIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) div->width = PCG_CORE_DIV_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) divider_ops = &clk_divider_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) mux_ops = &imx8m_clk_composite_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) } else if (composite_flags & IMX_COMPOSITE_BUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) div->shift = PCG_PREDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) div->width = PCG_PREDIV_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) divider_ops = &imx8m_clk_composite_divider_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) mux_ops = &imx8m_clk_composite_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) div->shift = PCG_PREDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) div->width = PCG_PREDIV_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) divider_ops = &imx8m_clk_composite_divider_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) mux_ops = &clk_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (!(composite_flags & IMX_COMPOSITE_FW_MANAGED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) flags |= CLK_SET_PARENT_GATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) div->lock = &imx_ccm_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) div->flags = CLK_DIVIDER_ROUND_CLOSEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) gate = kzalloc(sizeof(*gate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (!gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) gate_hw = &gate->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) gate->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) gate->bit_idx = PCG_CGC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) gate->lock = &imx_ccm_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) mux_hw, mux_ops, div_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) divider_ops, gate_hw, &clk_gate_ops, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) kfree(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) kfree(div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) kfree(mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return ERR_CAST(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) EXPORT_SYMBOL_GPL(imx8m_clk_hw_composite_flags);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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